src/device/pci_rom.c

@@ -178,7 +178,7 @@ static struct rom_header *check_initialized(const struct device *dev)
 	struct rom_header *run_rom;
 	struct pci_data *rom_data;
 
-	if (!CONFIG(VGA_ROM_RUN))
+	if (!CONFIG(VGA_ROM_RUN) && !CONFIG(RUN_FSP_GOP))
 		return NULL;
 
 	run_rom = (struct rom_header *)(uintptr_t)PCI_VGA_RAM_IMAGE_START;

src/device/pciexp_device.c

@@ -132,17 +132,17 @@ static void pciexp_config_max_latency(struct device *root, struct device *dev)
 	unsigned int cap;
 	cap = pciexp_find_extended_cap(dev, PCIE_EXT_CAP_LTR_ID);
 	if ((cap) && (root->ops->ops_pci != NULL) &&
-		(root->ops->ops_pci->set_L1_ss_latency != NULL))
-			root->ops->ops_pci->set_L1_ss_latency(dev, cap + 4);
+		(root->ops->ops_pci->set_ltr_max_latencies != NULL))
+			root->ops->ops_pci->set_ltr_max_latencies(dev, cap + 4);
 }
 
 static bool pciexp_is_ltr_supported(struct device *dev, unsigned int cap)
 {
 	unsigned int val;
 
-	val = pci_read_config16(dev, cap + PCI_EXP_DEV_CAP2_OFFSET);
+	val = pci_read_config16(dev, cap + PCI_EXP_DEVCAP2);
 
-	if (val & LTR_MECHANISM_SUPPORT)
+	if (val & PCI_EXP_DEVCAP2_LTR)
 		return true;
 
 	return false;
@@ -164,10 +164,10 @@ static void pciexp_configure_ltr(struct device *dev)
 		return;
 	}
 
-	cap += PCI_EXP_DEV_CTL_STS2_CAP_OFFSET;
+	cap += PCI_EXP_DEVCTL2;
 
 	/* Enable LTR for device */
-	pci_update_config32(dev, cap, ~LTR_MECHANISM_EN, LTR_MECHANISM_EN);
+	pci_update_config32(dev, cap, ~PCI_EXP_DEV2_LTR, PCI_EXP_DEV2_LTR);
 
 	/* Configure Max Snoop Latency */
 	pciexp_config_max_latency(dev->bus->dev, dev);

src/include/device/pci.h

@@ -31,7 +31,7 @@ struct pci_operations {
 	/* set the Subsystem IDs for the PCI device */
 	void (*set_subsystem)(struct device *dev, unsigned int vendor,
 		unsigned int device);
-	void (*set_L1_ss_latency)(struct device *dev, unsigned int off);
+	void (*set_ltr_max_latencies)(struct device *dev, unsigned int off);
 };
 
 struct pci_driver {

src/include/device/pci_def.h

@@ -386,12 +386,6 @@
 #define PCI_EXP_DEVCAP		4	/* Device capabilities */
 #define  PCI_EXP_DEVCAP_PAYLOAD	0x07	/* Max_Payload_Size */
 #define  PCI_EXP_DEVCAP_PHANTOM	0x18	/* Phantom functions */
-#define PCI_EXP_DEV_CAP2_OFFSET	0x24	/* Device Capabilities 2 offset */
-/* LTR mechanism supported.Bit 11 of Device Cap 2 Register */
-#define  LTR_MECHANISM_SUPPORT	(1 << 11)
-#define PCI_EXP_DEV_CTL_STS2_CAP_OFFSET	0x28	/* Device Control 2  offset */
-/* LTR mechanism enable. Bit 10 of Device Control 2 Register */
-#define  LTR_MECHANISM_EN	(1 << 10)
 #define  PCI_EXP_DEVCAP_EXT_TAG	0x20	/* Extended tags */
 #define  PCI_EXP_DEVCAP_L0S	0x1c0	/* L0s Acceptable Latency */
 #define  PCI_EXP_DEVCAP_L1	0xe00	/* L1 Acceptable Latency */
@@ -445,6 +439,10 @@
 #define  PCI_EXP_RTCTL_CRSSVE	0x10	/* CRS Software Visibility Enable */
 #define PCI_EXP_RTCAP		30	/* Root Capabilities */
 #define PCI_EXP_RTSTA		32	/* Root Status */
+#define PCI_EXP_DEVCAP2		36	/* Device capabilities 2 */
+#define  PCI_EXP_DEVCAP2_LTR	0x0800	/* LTR supported */
+#define PCI_EXP_DEVCTL2		40	/* Device Control 2 */
+#define  PCI_EXP_DEV2_LTR	0x0400	/* LTR enabled */
 
 /* Extended Capabilities (PCI-X 2.0 and Express) */
 #define PCI_EXT_CAP_ID(header)		(header & 0x0000ffff)

src/mainboard/google/guybrush/Makefile.inc

@@ -2,10 +2,20 @@
 
 bootblock-y += bootblock.c
 
+ifneq ($(wildcard $(MAINBOARD_BLOBS_DIR)/APCB_CZN_D4.bin),)
+$(info APCB sources present.)
+APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_CZN_D4.bin
+APCB_SOURCES_RECOVERY = $(MAINBOARD_BLOBS_DIR)/APCB_CZN_D4.bin
+else
+$(info APCB sources not found.  Skipping APCB.)
+endif
+
 ramstage-y += mainboard.c
 ramstage-y += ec.c
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 
+verstage-y += verstage.c
+
 subdirs-y += variants/baseboard
 subdirs-y += variants/$(VARIANT_DIR)
 

src/mainboard/google/guybrush/bootblock.c

@@ -11,8 +11,10 @@ void bootblock_mainboard_early_init(void)
 	size_t num_gpios;
 	const struct soc_amd_gpio *gpios;
 
-	gpios = variant_bootblock_gpio_table(&num_gpios);
-	program_gpios(gpios, num_gpios);
+	if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) {
+		gpios = variant_early_gpio_table(&num_gpios);
+		program_gpios(gpios, num_gpios);
+	}
 
 	if (CONFIG(GPIO_SIGN_OF_LIFE)) {
 		for (int x = 0; x < 20; x++) {

src/mainboard/google/guybrush/dsdt.asl

 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <acpi/acpi.h>
+#include <variant/ec.h>
+
 DefinitionBlock (
 	"dsdt.aml",
 	"DSDT",
@@ -11,6 +13,14 @@ DefinitionBlock (
 	)
 {
 	#include <acpi/dsdt_top.asl>
-
 	#include <soc.asl>
+
+	/* Chrome OS Embedded Controller */
+	Scope (\_SB.PCI0.LPCB)
+	{
+		/* ACPI code for EC SuperIO functions */
+		#include <ec/google/chromeec/acpi/superio.asl>
+		/* ACPI code for EC functions */
+		#include <ec/google/chromeec/acpi/ec.asl>
+	}
 }

src/mainboard/google/guybrush/variants/baseboard/Makefile.inc

@@ -2,4 +2,6 @@ bootblock-y += gpio.c
 
 ramstage-y += gpio.c
 
+verstage-y += gpio.c
+
 smm-y += gpio.c

src/mainboard/google/guybrush/variants/baseboard/gpio.c

@@ -108,16 +108,7 @@ static const struct soc_amd_gpio base_gpio_table[] = {
 	/* CLK_REQ0_L */
 	PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE),
 	/* GPIO_93 - GPIO_103: Not available */
-	/* ESPI1_DATA0 */
-	PAD_NF(GPIO_104, SPI2_DO_ESPI2_D0, PULL_NONE),
-	/* ESPI1_DATA1 */
-	PAD_NF(GPIO_105, SPI2_DI_ESPI2_D1, PULL_NONE),
-	/* ESPI1_DATA2 */
-	PAD_NF(GPIO_106, EMMC_SPI2_WP_L_ESPI2_D2, PULL_NONE),
-	/* ESPI1_DATA3 */
-	PAD_NF(GPIO_107, SPI2_HOLD_L_ESPI2_D3, PULL_NONE),
-	/* ESPI_ALERT_L */
-	PAD_NF(GPIO_108, ESPI_ALERT_D1, PULL_NONE),
+	/* GPIO_104 - GPIO_108: eSPI configured in early stage */
 	/* RAM_ID_0 / DEV_BEEP_EN */
 	PAD_GPI(GPIO_109, PULL_NONE),
 	/* GPIO_110 - GPIO_112: Not available */
@@ -163,9 +154,18 @@ static const struct soc_amd_gpio base_gpio_table[] = {
 	PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE),
 };
 
-/* Early GPIO configuration in bootblock */
-static const struct soc_amd_gpio bootblock_gpio_table[] = {
-	/* TODO: Fill bootblock gpio configuration */
+/* Early GPIO configuration */
+static const struct soc_amd_gpio early_gpio_table[] = {
+	/* ESPI1_DATA0 */
+	PAD_NF(GPIO_104, SPI2_DO_ESPI2_D0, PULL_NONE),
+	/* ESPI1_DATA1 */
+	PAD_NF(GPIO_105, SPI2_DI_ESPI2_D1, PULL_NONE),
+	/* ESPI1_DATA2 */
+	PAD_NF(GPIO_106, EMMC_SPI2_WP_L_ESPI2_D2, PULL_NONE),
+	/* ESPI1_DATA3 */
+	PAD_NF(GPIO_107, SPI2_HOLD_L_ESPI2_D3, PULL_NONE),
+	/* ESPI_ALERT_L */
+	PAD_NF(GPIO_108, ESPI_ALERT_D1, PULL_NONE),
 };
 
 /* GPIO configuration for sleep */
@@ -184,10 +184,10 @@ const struct soc_amd_gpio *__weak variant_override_gpio_table(size_t *size)
 	return NULL;
 }
 
-const struct soc_amd_gpio *__weak variant_bootblock_gpio_table(size_t *size)
+const struct soc_amd_gpio *__weak variant_early_gpio_table(size_t *size)
 {
-	*size = ARRAY_SIZE(bootblock_gpio_table);
-	return bootblock_gpio_table;
+	*size = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
 }
 
 const __weak struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size)

src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h

@@ -6,6 +6,7 @@
 #include <ec/ec.h>
 #include <ec/google/chromeec/ec_commands.h>
 #include <baseboard/gpio.h>
+#include <soc/gpio.h>
 
 #define MAINBOARD_EC_SCI_EVENTS                                                                \
 	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)                                          \
@@ -45,4 +46,37 @@
 	 | EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)                                  \
 	 | EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
 
+/*
+ * ACPI related definitions for ASL code.
+ */
+
+/* Set GPI for SCI */
+#define EC_SCI_GPI GEVENT_24 /* eSPI system event -> GPE 24 */
+
+/* Enable EC backed ALS device in ACPI */
+#define EC_ENABLE_ALS_DEVICE
+
+/* Enable LID switch and provide wake pin for EC */
+#define EC_ENABLE_LID_SWITCH
+#define EC_ENABLE_WAKE_PIN GEVENT_3 /* AGPIO 22 -> GPE 3 */
+
+/* Enable Tablet switch */
+#define EC_ENABLE_TBMC_DEVICE
+
+#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
+#define SIO_EC_HOST_ENABLE   /* EC Host Interface Resources */
+#define SIO_EC_ENABLE_PS2K   /* Enable PS/2 Keyboard */
+
+/* Enable EC sync interrupt */
+#define EC_ENABLE_SYNC_IRQ_GPIO
+
+/* EC sync irq */
+#define EC_SYNC_IRQ GPIO_84
+
+/* Enable EC backed PD MCU device in ACPI */
+#define EC_ENABLE_PD_MCU_DEVICE
+
+/* Enable EC backed Keyboard Backlight in ACPI */
+#define EC_ENABLE_KEYBOARD_BACKLIGHT
+
 #endif /* __MAINBOARD_EC_H__ */

src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h

@@ -18,8 +18,8 @@ const struct soc_amd_gpio *variant_base_gpio_table(size_t *size);
  */
 const struct soc_amd_gpio *variant_override_gpio_table(size_t *size);
 
-/* This function provides GPIO init in bootblock. */
-const struct soc_amd_gpio *variant_bootblock_gpio_table(size_t *size);
+/* This function provides early GPIO init in bootblock or psp. */
+const struct soc_amd_gpio *variant_early_gpio_table(size_t *size);
 
 /* This function provides GPIO settings before entering sleep. */
 const struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size);

src/mainboard/google/guybrush/verstage.c

+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <amdblocks/gpio_banks.h>
+#include <baseboard/variants.h>
+#include <security/vboot/vboot_common.h>
+
+static void setup_gpio(void)
+{
+	const struct soc_amd_gpio *gpios;
+	size_t num_gpios;
+
+	if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) {
+		gpios = variant_early_gpio_table(&num_gpios);
+		program_gpios(gpios, num_gpios);
+	}
+}
+
+void verstage_mainboard_early_init(void)
+{
+	setup_gpio();
+}
+
+void verstage_mainboard_init(void)
+{
+}

src/soc/amd/cezanne/Makefile.inc

@@ -35,6 +35,7 @@ ramstage-y	+= pcie_gpp.c
 ramstage-y	+= reset.c
 ramstage-y	+= root_complex.c
 ramstage-y	+= uart.c
+ramstage-y	+= xhci.c
 
 smm-y		+= gpio.c
 smm-y		+= smihandler.c

src/soc/amd/cezanne/acpi/soc.asl

 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include "globalnvs.asl"
+
 Scope(\_SB) {
 	/* global utility methods expected within the \_SB scope */
 	#include <arch/x86/acpi/globutil.asl>
 
 	#include <soc/amd/common/acpi/gpio_bank_lib.asl>
 
-	#include "globalnvs.asl"
-
 	#include "pci_int_defs.asl"
 
 	#include "mmio.asl"

src/soc/amd/cezanne/fsp_params.c

 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <fsp/api.h>
+#include <device/pci.h>
+
+static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg)
+{
+	scfg->vbios_buffer_addr = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0;
+}
 
 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 {
+	FSP_S_CONFIG *scfg = &supd->FspsConfig;
+
+	fsp_assign_vbios_upds(scfg);
 }

src/soc/amd/cezanne/xhci.c

+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/gpio_banks.h>
+#include <amdblocks/smi.h>
+#include <bootstate.h>
+#include <device/device.h>
+#include <drivers/usb/pci_xhci/pci_xhci.h>
+#include <soc/pci_devs.h>
+#include <soc/smi.h>
+
+static const struct sci_source xhci_sci_sources[] = {
+	{
+		.scimap = SMITYPE_XHC0_PME,
+		.gpe = GEVENT_31,
+		.direction = SMI_SCI_LVL_HIGH,
+		.level = SMI_SCI_EDG
+	},
+	{
+		.scimap = SMITYPE_XHC1_PME,
+		.gpe = GEVENT_31,
+		.direction = SMI_SCI_LVL_HIGH,
+		.level = SMI_SCI_EDG
+	}
+};
+
+enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe)
+{
+	if (dev->bus->dev->path.type != DEVICE_PATH_PCI)
+		return CB_ERR_ARG;
+
+	if (dev->bus->dev->path.pci.devfn != PCIE_ABC_A_DEVFN)
+		return CB_ERR_ARG;
+
+	if (dev->path.type != DEVICE_PATH_PCI)
+		return CB_ERR_ARG;
+
+	if (dev->path.pci.devfn == XHCI0_DEVFN)
+		*gpe = xhci_sci_sources[0].gpe;
+	else if (dev->path.pci.devfn == XHCI1_DEVFN)
+		*gpe = xhci_sci_sources[1].gpe;
+	else
+		return CB_ERR_ARG;
+
+	return CB_SUCCESS;
+}
+
+static void configure_xhci_sci(void *unused)
+{
+	gpe_configure_sci(xhci_sci_sources, ARRAY_SIZE(xhci_sci_sources));
+}
+
+BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, configure_xhci_sci, NULL);

src/soc/amd/common/block/graphics/graphics.c

@@ -7,6 +7,7 @@
 #include <console/console.h>
 #include <fsp/graphics.h>
 #include <soc/intel/common/vbt.h>
+#include <timestamp.h>
 
 #define ATIF_FUNCTION_VERIFY_INTERFACE 0x0
 struct atif_verify_interface_output {
@@ -129,6 +130,25 @@ void *vbt_get(void)
 	return NULL;
 }
 
+static void graphics_set_resources(struct device *const dev)
+{
+	struct rom_header *rom, *ram;
+
+	pci_dev_set_resources(dev);
+
+	if (!CONFIG(RUN_FSP_GOP))
+		return;
+
+	timestamp_add_now(TS_OPROM_INITIALIZE);
+	rom = pci_rom_probe(dev);
+	if (rom == NULL)
+		return;
+	ram = pci_rom_load(dev, rom);
+	if (ram == NULL)
+		return;
+	timestamp_add_now(TS_OPROM_COPY_END);
+}
+
 static void graphics_dev_init(struct device *const dev)
 {
 	if (CONFIG(RUN_FSP_GOP)) {
@@ -147,7 +167,7 @@ static void graphics_dev_init(struct device *const dev)
 
 static const struct device_operations graphics_ops = {
 	.read_resources		= pci_dev_read_resources,
-	.set_resources		= pci_dev_set_resources,
+	.set_resources		= graphics_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
 	.init			= graphics_dev_init,
 	.ops_pci		= &pci_dev_ops_pci,
@@ -158,6 +178,7 @@ static const struct device_operations graphics_ops = {
 
 static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_ATI_FAM17H_MODEL18H_GPU,
+	PCI_DEVICE_ID_ATI_FAM19H_MODEL51H_GPU,
 	0,
 };
 

src/soc/amd/common/block/include/amdblocks/chip.h

@@ -5,6 +5,7 @@
 
 #include <amdblocks/espi.h>
 #include <amdblocks/spi.h>
+#include <stdint.h>
 
 struct soc_amd_common_config {
 	/*

src/soc/amd/common/block/include/amdblocks/psp.h

@@ -3,6 +3,8 @@
 #ifndef AMD_BLOCK_PSP_H
 #define AMD_BLOCK_PSP_H
 
+#include <stdint.h>
+
 /* Get the mailbox base address - specific to family of device. */
 void *soc_get_mbox_address(void);
 

src/soc/amd/common/block/include/amdblocks/smi.h

@@ -3,7 +3,7 @@
 #ifndef AMD_BLOCK_SMI_H
 #define AMD_BLOCK_SMI_H
 
-#include <stdint.h>
+#include <types.h>
 
 enum smi_mode {
 	SMI_MODE_DISABLE = 0,

src/soc/amd/picasso/fsp_params.c

@@ -9,6 +9,7 @@
 #include <soc/soc_util.h>
 #include <fsp/api.h>
 #include "chip.h"
+#include <device/pci.h>
 
 static void fsps_update_emmc_config(FSP_S_CONFIG *scfg,
 				const struct soc_amd_picasso_config *cfg)
@@ -175,7 +176,11 @@ static void fsp_edp_tuning_upds(FSP_S_CONFIG *scfg,
 		scfg->pwrdown_bloff_to_varybloff = cfg->pwrdown_bloff_to_varybloff;
 		scfg->min_allowed_bl_level = cfg->min_allowed_bl_level;
 	}
+}
 
+static void fsp_assign_vbios_upds(FSP_S_CONFIG *scfg)
+{
+	scfg->vbios_buffer_addr = CONFIG(RUN_FSP_GOP) ? PCI_VGA_RAM_IMAGE_START : 0;
 }
 
 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
@@ -189,4 +194,5 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	fsp_assign_ioapic_upds(scfg);
 	fsp_usb_oem_customization(scfg, cfg);
 	fsp_edp_tuning_upds(scfg, cfg);
+	fsp_assign_vbios_upds(scfg);
 }

src/soc/intel/broadwell/pch/pcie.c

@@ -609,7 +609,7 @@ static void pch_pcie_enable(struct device *dev)
 		root_port_commit_config();
 }
 
-static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int off)
+static void pcie_set_ltr_max_latencies(struct device *dev, unsigned int off)
 {
 	/* Set max snoop and non-snoop latency for Broadwell */
 	pci_write_config32(dev, off,
@@ -619,7 +619,7 @@ static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int off)
 
 static struct pci_operations pcie_ops = {
 	.set_subsystem = pci_dev_set_subsystem,
-	.set_L1_ss_latency = pcie_set_L1_ss_max_latency,
+	.set_ltr_max_latencies = pcie_set_ltr_max_latencies,
 };
 
 static struct device_operations device_ops = {

src/soc/intel/common/block/pcie/pcie.c

@@ -45,7 +45,7 @@ static void pch_pcie_init(struct device *dev)
 	pci_write_config16(dev, PCI_SEC_STATUS, reg16);
 }
 
-static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int offset)
+static void pcie_set_ltr_max_latencies(struct device *dev, unsigned int offset)
 {
 	/* Set max snoop and non-snoop latency for the SOC */
 	pci_write_config32(dev, offset,
@@ -54,7 +54,7 @@ static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int offset)
 }
 
 static struct pci_operations pcie_ops = {
-	.set_L1_ss_latency = pcie_set_L1_ss_max_latency,
+	.set_ltr_max_latencies = pcie_set_ltr_max_latencies,
 	.set_subsystem = pci_dev_set_subsystem,
 };
 

src/vendorcode/amd/fsp/cezanne/FspsUpd.h

@@ -51,8 +51,8 @@ typedef struct __packed {
 	/** Offset 0x0128**/	uint8_t                     gnb_ioapic_id;
 	/** Offset 0x0129**/	uint8_t                     fch_ioapic_id;
 	/** Offset 0x012A**/	uint8_t                     UnusedUpdSpace0[6];
-	/** Offset 0x0130**/	uint8_t                     unused4[16];
-	/** Offset 0x0140**/	uint8_t                     UnusedUpdSpace1[16];
+	/** Offset 0x0130**/	uint32_t                    vbios_buffer_addr;
+	/** Offset 0x0134**/    uint8_t                     UnusedUpdSpace1[28];
 	/** Offset 0x0150**/	uint16_t                    UpdTerminator;
 } FSP_S_CONFIG;
 

src/vendorcode/amd/fsp/picasso/FspsUpd.h

@@ -65,7 +65,9 @@ typedef struct __packed {
 	/** Offset 0x014A**/	uint8_t                     usb_3_rx_vref_ctrl_en_x;
 	/** Offset 0x014B**/	uint8_t                     usb_3_tx_vboost_lvl_x;
 	/** Offset 0x014C**/	uint8_t                     usb_3_tx_vboost_lvl_en_x;
-	/** Offset 0x014D**/	uint8_t                     UnusedUpdSpace0[179];
+	/** Offset 0x014D**/	uint8_t                     UnusedUpdSpace0[3];
+	/** Offset 0x0150**/	uint32_t                    vbios_buffer_addr;
+	/** Offset 0x0154**/	uint8_t                     UnusedUpdSpace1[172];
 	/** Offset 0x0200**/	uint16_t                    UpdTerminator;
 } FSP_S_CONFIG;
 

util/qemu/q35-alpine.cfg

+# Try to resemble an Alpine Ridge topology
+[device "alpine-root"]
+	driver = "x3130-upstream"
+	bus = "ich9-pcie-port-1"
+	addr = "00.0"
+
+[device "alpine-0"]
+		driver = "xio3130-downstream"
+		bus = "alpine-root"
+		addr = "00.0"
+		chassis = "10"
+
+[device "alpine-nhi"]
+			driver = "pci-testdev"
+			bus = "alpine-0"
+			addr = "00.0"
+			membar = "1M"
+
+[device "alpine-1"]
+		driver = "xio3130-downstream"
+		bus = "alpine-root"
+		addr = "01.0"
+		chassis = "11"
+
+[device "alpine-up"]
+			driver = "x3130-upstream"
+			bus = "alpine-1"
+			addr = "00.0"
+
+[device "alpine-down0"]
+				driver = "xio3130-downstream"
+				bus = "alpine-up"
+				addr = "00.0"
+				chassis = "20"
+
+#					TBT device here
+
+[device "alpine-down1"]
+				driver = "xio3130-downstream"
+				bus = "alpine-up"
+				addr = "01.0"
+				chassis = "21"
+
+#					TBT device here
+
+[device "alpine-down4"]
+				driver = "xio3130-downstream"
+				bus = "alpine-up"
+				addr = "04.0"
+				chassis = "24"
+
+[device "alpine-xhci"]
+					driver = "nec-usb-xhci"
+					bus = "alpine-down4"
+					addr = "00.0"
+
+[device "alpine-2"]
+		driver = "xio3130-downstream"
+		bus = "alpine-root"
+		addr = "02.0"
+		chassis = "12"