blobs @ 4fdfa1c7

-Subproject commit 02ab6c66480ccd5f6bdfddd6fa090156d436fa4b
+Subproject commit 4fdfa1c797c9c970073c6de23984a7be716ba949

src/mainboard/amd/inagua/Kconfig

@@ -39,10 +39,6 @@ config ONBOARD_VGA_IS_PRIMARY
 	bool
 	default y
 
-config VGA_BIOS
-	bool
-	default n
-
 #config VGA_BIOS_FILE
 #        string "VGA BIOS path and filename"
 #        depends on VGA_BIOS

src/mainboard/amd/majolica/Makefile.inc

@@ -3,8 +3,7 @@
 bootblock-y += bootblock.c
 bootblock-y += early_gpio.c
 
-APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_CZN_D4_Updatable.bin
-APCB_SOURCES_68 = $(MAINBOARD_BLOBS_DIR)/APCB_CZN_D4_Updatable_68.bin
+APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_CZN_D4.bin
 APCB_SOURCES_RECOVERY = $(MAINBOARD_BLOBS_DIR)/APCB_CZN_D4_DefaultRecovery.bin
 
 ifeq ($(CONFIG_MAJOLICA_HAVE_MCHP_FW),y)

src/mainboard/amd/padmelon/Kconfig

@@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select SUPERIO_FINTEK_COMMON_PRE_RAM
 	select SUPERIO_FINTEK_FAN_CONTROL
 	select SUPERIO_FINTEK_FAN_API_CALL
-	select VGA_BIOS
 	select AZALIA_PLUGIN_SUPPORT
 
 config MAINBOARD_DIR
@@ -49,6 +48,9 @@ config IRQ_SLOT_COUNT
 	int
 	default 11
 
+config VGA_BIOS
+	default y if USE_AMD_BLOBS
+
 config HWM_PORT
 	hex
 	default 0x0225

src/mainboard/amd/persimmon/Kconfig

@@ -40,10 +40,6 @@ config ONBOARD_VGA_IS_PRIMARY
 	bool
 	default y
 
-config VGA_BIOS
-	bool
-	default n
-
 #config VGA_BIOS_FILE
 #	string "VGA BIOS path and filename"
 #	depends on VGA_BIOS

src/mainboard/amd/south_station/Kconfig

@@ -39,9 +39,6 @@ config ONBOARD_VGA_IS_PRIMARY
 	bool
 	default y
 
-config VGA_BIOS
-	bool
-	default n
 config VGA_BIOS_FILE
 	string
 	default "site-local/vgabios.bin"

src/mainboard/amd/union_station/Kconfig

@@ -38,9 +38,6 @@ config ONBOARD_VGA_IS_PRIMARY
 	bool
 	default y
 
-config VGA_BIOS
-	bool
-	default n
 config VGA_BIOS_FILE
 	string
 	default "site-local/vgabios.bin"

src/mainboard/elmex/pcm205400/Kconfig

@@ -48,10 +48,6 @@ config ONBOARD_VGA_IS_PRIMARY
 	bool
 	default y
 
-config VGA_BIOS
-	bool
-	default n
-
 config SB800_AHCI_ROM
 	bool
 	default n

src/mainboard/gizmosphere/gizmo/Kconfig

@@ -40,10 +40,6 @@ config ONBOARD_VGA_IS_PRIMARY
 	bool
 	default y
 
-config VGA_BIOS
-	bool
-	default n
-
 config VGA_BIOS_ID
 	string
 	default "1002,9804"

src/mainboard/google/guybrush/variants/baseboard/devicetree.cb

@@ -42,5 +42,11 @@ chip soc/amd/cezanne
 		device ref gpp_bridge_a on  # Internal GPP Bridge 0 to Bus A
 			device ref gfx on end # Internal GPU (GFX)
 		end
+
+		device ref lpc_bridge on
+			chip ec/google/chromeec
+				device pnp 0c09.0 on end
+			end
+		end
 	end # domain
 end	# chip soc/amd/cezanne

src/mainboard/google/zork/Kconfig

@@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select SOC_AMD_COMMON_BLOCK_USE_ESPI
 	select SOC_AMD_PICASSO
 	select SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF
-	select VGA_BIOS
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_AMD_I2S_MACHINE_DEV
 	select DISABLE_SPI_FLASH_ROM_SHARING
@@ -105,6 +104,9 @@ config ONBOARD_VGA_IS_PRIMARY
 	bool
 	default y
 
+config VGA_BIOS
+	default y if USE_AMD_BLOBS
+
 config VBOOT
 	select EC_GOOGLE_CHROMEEC_SWITCHES
 	select VBOOT_LID_SWITCH

src/mainboard/google/zork/Makefile.inc

@@ -4,6 +4,7 @@ bootblock-y += bootblock.c
 
 romstage-y += chromeos.c
 romstage-y += sku_id.c
+romstage-y += romstage.c
 
 ramstage-y += chromeos.c
 ramstage-y += ec.c

src/mainboard/google/zork/romstage.c

+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <soc/romstage.h>
+
+void __weak variant_updm_update(FSP_M_CONFIG *mcfg) {}
+
+void mainboard_updm_update(FSP_M_CONFIG *mcfg)
+{
+	variant_updm_update(mcfg);
+}

src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb

 # SPDX-License-Identifier: GPL-2.0-or-later
+fw_config
+	field TOUCHPAD 26
+		option REGULAR_TOUCHPAD 1
+		option NUMPAD_TOUCHPAD 0
+	end
+end
+
 chip soc/amd/picasso
 
 	# Set FADT Configuration

src/mainboard/google/zork/variants/baseboard/helpers.c

@@ -43,6 +43,9 @@ enum {
 	/* SAR presence */
 	FW_CONFIG_MASK_SAR = 0x7,
 	FW_CONFIG_SHIFT_SAR = 23,
+	/* Mainboard Type for VCORE IC */
+	FW_CONFIG_MASK_MB_TYPE = 0x1,
+	FW_CONFIG_SHIFT_MB_TYPE = 26,
 	/* Fan information */
 	FW_CONFIG_MASK_FAN = 0x3,
 	FW_CONFIG_SHIFT_FAN = 27,
@@ -86,6 +89,11 @@ int variant_gets_sar_config(void)
 	return extract_field(FW_CONFIG_MASK_SAR, FW_CONFIG_SHIFT_SAR);
 }
 
+int variant_gets_mb_type_config(void)
+{
+	return extract_field(FW_CONFIG_MASK_MB_TYPE, FW_CONFIG_SHIFT_MB_TYPE);
+}
+
 int variant_has_emmc(void)
 {
 	return !!extract_field(FW_CONFIG_MASK_EMMC, FW_CONFIG_SHIFT_EMMC);

src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h

@@ -20,10 +20,10 @@
 #endif /* _ACPI__ */
 
 /* These define the GPE, not the GPIO. */
-#define EC_SCI_GPI		3	/* eSPI system event -> GPE 3 */
-#define EC_WAKE_GPI		15	/* AGPIO 24 -> GPE 15 */
+#define EC_SCI_GPI		GEVENT_3	/* AGPIO 22 -> GPE 3 */
+#define EC_WAKE_GPI		GEVENT_15	/* AGPIO 24 -> GPE 15 */
 
 /* EC sync irq */
-#define EC_SYNC_IRQ		31
+#define EC_SYNC_IRQ		GPIO_31
 
 #endif /* __BASEBOARD_GPIO_H__ */

src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h

@@ -6,6 +6,7 @@
 #include <stddef.h>
 #include <boardid.h>
 #include <ec/google/chromeec/ec.h>
+#include <FspmUpd.h>
 #include <soc/platform_descriptors.h>
 #include "chip.h"
 
@@ -32,6 +33,8 @@ const struct soc_amd_gpio *variant_bootblock_gpio_table(size_t *size, int slp_ty
  */
 const struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size, int slp_typ);
 
+void variant_updm_update(FSP_M_CONFIG *mcfg);
+
 /* Program any required GPIOs at the finalize phase */
 void finalize_gpios(int slp_typ);
 /* Modify devictree settings during ramstage. */
@@ -61,6 +64,8 @@ const fsp_ddi_descriptor *baseboard_get_ddi_descriptors(size_t *num);
 /* Retrieve attributes from FW_CONFIG in CBI. */
 /* Return value of SAR config. */
 int variant_gets_sar_config(void);
+/* Return value of Mainboard Type config */
+int variant_gets_mb_type_config(void);
 /* Return 0 if non-existent, 1 if present. */
 int variant_has_emmc(void);
 /* Return 0 if non-existent, 1 if present. */

src/mainboard/google/zork/variants/shuboz/overridetree.cb

@@ -29,6 +29,7 @@ chip soc/amd/picasso
 		.speed = I2C_SPEED_FAST,
 		.rise_time_ns = 18,  /* 0 to 2.31 (3.3 * .7) */
 		.fall_time_ns = 57,  /* 2.31 to 0 */
+		.data_hold_time_ns = 335,
 	}"
 
 	# I2C3 for H1
@@ -59,14 +60,26 @@ chip soc/amd/picasso
 			register "disable_gpio_export_in_crs" = "1"
 			device i2c 10 on end
 		end
+		chip drivers/i2c/generic
+			register "hid" = ""ELAN0000""
+			register "desc" = ""ELAN Touchpad""
+			register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)"
+			register "wake" = "GEVENT_22"
+			register "probed" = "1"
+			device i2c 15 on
+				probe TOUCHPAD REGULAR_TOUCHPAD
+			end
+		end
 		chip drivers/i2c/hid
-				register "generic.hid" = ""ELAN2702""
-				register "generic.desc" = ""ELAN Touchpad""
-				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)"
-				register "generic.wake" = "GEVENT_22"
-				register "generic.probed" = "1"
-				register "hid_desc_reg_offset" = "0x01"
-				device i2c 15 on end
+			register "generic.hid" = ""ELAN2702""
+			register "generic.desc" = ""ELAN Touchpad""
+			register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)"
+			register "generic.wake" = "GEVENT_22"
+			register "generic.probed" = "1"
+			register "hid_desc_reg_offset" = "0x01"
+			device i2c 15 on
+				probe TOUCHPAD NUMPAD_TOUCHPAD
+			end
 		end
 	end # device
 end	# chip soc/amd/picasso

src/mainboard/google/zork/variants/vilboz/Makefile.inc

@@ -2,5 +2,7 @@
 
 subdirs-y += ./spd
 
+romstage-y += romstage.c
+
 ramstage-y += variant.c
 ramstage-y += gpio.c

src/mainboard/google/zork/variants/vilboz/romstage.c

+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <console/console.h>
+
+void variant_updm_update(FSP_M_CONFIG *mcfg)
+{
+	printk(BIOS_INFO, "%s UPDM update\n", __func__);
+	if (variant_gets_mb_type_config()) {
+		mcfg->telemetry_vddcr_vdd_slope_mA = 32453;
+		mcfg->telemetry_vddcr_vdd_offset = 168;
+		mcfg->telemetry_vddcr_soc_slope_mA = 22644;
+		mcfg->telemetry_vddcr_soc_offset = -70;
+	}
+}

src/mainboard/jetway/nf81-t56n-lf/Kconfig

@@ -40,10 +40,6 @@ config ONBOARD_VGA_IS_PRIMARY
 	bool
 	default y
 
-config VGA_BIOS
-	bool
-	default n
-
 #config VGA_BIOS_FILE
 #	string "VGA BIOS path and filename"
 #	depends on VGA_BIOS

src/mainboard/lippert/frontrunner-af/Kconfig

@@ -55,10 +55,6 @@ config ONBOARD_VGA_IS_PRIMARY
 	bool
 	default y
 
-config VGA_BIOS
-	bool
-	default n
-
 config VGA_BIOS_ID
 	string
 	default "1002,9802"

src/mainboard/pcengines/apu1/Kconfig

@@ -43,10 +43,6 @@ config ONBOARD_VGA_IS_PRIMARY
 	bool
 	default y
 
-config VGA_BIOS
-	bool
-	default n
-
 #config VGA_BIOS_FILE
 #	string "VGA BIOS path and filename"
 #	depends on VGA_BIOS

src/soc/amd/cezanne/Kconfig

@@ -15,6 +15,8 @@ config SOC_SPECIFIC_OPTIONS
 	select ARCH_ROMSTAGE_X86_32
 	select ARCH_RAMSTAGE_X86_32
 	select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
+	select DRIVERS_USB_ACPI
+	select DRIVERS_USB_PCI_XHCI
 	select FSP_COMPRESS_FSP_M_LZMA
 	select FSP_COMPRESS_FSP_S_LZMA
 	select HAVE_ACPI_TABLES

src/soc/amd/cezanne/Makefile.inc

@@ -97,7 +97,7 @@ endif
 #
 
 # type = 0x60
-PSP_APCB_FILES=$(APCB_SOURCES) $(APCB_SOURCES_68) $(APCB_SOURCES_RECOVERY)
+PSP_APCB_FILES=$(APCB_SOURCES) $(APCB_SOURCES_RECOVERY)
 
 # type = 0x61
 PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS)

src/soc/amd/cezanne/chipset.cb

@@ -25,8 +25,56 @@ chip soc/amd/cezanne
 			device pci 0.0 alias gfx off end # Internal GPU (GFX)
 			device pci 0.1 alias gfx_hda off end # Display HD Audio Controller (GFXAZ)
 			device pci 0.2 alias crypto off end # Crypto Coprocessor
-			device pci 0.3 alias xhci_0 off end
-			device pci 0.4 alias xhci_1 off end
+			device pci 0.3 alias xhci_0 off
+				chip drivers/usb/acpi
+					register "type" = "UPC_TYPE_HUB"
+					device usb 0.0 alias xhci_0_root_hub off
+						chip drivers/usb/acpi
+							device usb 3.0 alias usb3_port0 off end
+						end
+						chip drivers/usb/acpi
+							device usb 3.1 alias usb3_port1 off end
+						end
+						chip drivers/usb/acpi
+							device usb 2.0 alias usb2_port0 off end
+						end
+						chip drivers/usb/acpi
+							device usb 2.1 alias usb2_port1 off end
+						end
+						chip drivers/usb/acpi
+							device usb 2.2 alias usb2_port2 off end
+						end
+						chip drivers/usb/acpi
+							device usb 2.3 alias usb2_port3 off end
+						end
+					end
+				end
+			end
+			device pci 0.4 alias xhci_1 off
+				chip drivers/usb/acpi
+					register "type" = "UPC_TYPE_HUB"
+					device usb 0.0 alias xhci_1_root_hub off
+						chip drivers/usb/acpi
+							device usb 3.0 alias usb3_port4 off end
+						end
+						chip drivers/usb/acpi
+							device usb 3.1 alias usb3_port5 off end
+						end
+						chip drivers/usb/acpi
+							device usb 2.0 alias usb2_port4 off end
+						end
+						chip drivers/usb/acpi
+							device usb 2.1 alias usb2_port5 off end
+						end
+						chip drivers/usb/acpi
+							device usb 2.2 alias usb2_port6 off end
+						end
+						chip drivers/usb/acpi
+							device usb 2.3 alias usb2_port7 off end
+						end
+					end
+				end
+			end
 			device pci 0.5 alias acp off end # Audio Processor (ACP)
 			device pci 0.6 alias hda off end # Audio Processor HD Audio Controller (main AZ)
 			device pci 0.7 alias mp2 off end # Sensor Fusion Hub (MP2)

src/soc/amd/common/block/graphics/graphics.c

@@ -6,6 +6,7 @@
 #include <device/pci_ids.h>
 #include <console/console.h>
 #include <fsp/graphics.h>
+#include <soc/intel/common/vbt.h>
 
 #define ATIF_FUNCTION_VERIFY_INTERFACE 0x0
 struct atif_verify_interface_output {
@@ -118,6 +119,16 @@ static const char *graphics_acpi_name(const struct device *dev)
 	return "IGFX";
 }
 
+/*
+ * Even though AMD does not need VBT we still need to implement the
+ * vbt_get() function to not break the build with GOP driver enabled
+ * (see fsps_return_value_handler() in fsp2_0/silicon_init.c
+ */
+void *vbt_get(void)
+{
+	return NULL;
+}
+
 static void graphics_dev_init(struct device *const dev)
 {
 	if (CONFIG(RUN_FSP_GOP)) {

src/soc/amd/picasso/Makefile.inc

@@ -137,8 +137,7 @@ ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y)
 # type = 0x6B - PSP Shared memory location
 ifneq ($(CONFIG_PSP_SHAREDMEM_SIZE),0x0)
 PSP_SHAREDMEM_SIZE=$(CONFIG_PSP_SHAREDMEM_SIZE)
-_PSP_SHAREDMEM_BASE=$(shell grep _psp_sharedmem_dram $(obj)/cbfs/$(CONFIG_CBFS_PREFIX)/bootblock.map | cut -f1 -d' ')
-PSP_SHAREDMEM_BASE=$(shell printf "0x%s" $(_PSP_SHAREDMEM_BASE))
+PSP_SHAREDMEM_BASE=$(shell awk '$$3 == "_psp_sharedmem_dram" {printf "0x" $$1}' $(objcbfs)/bootblock.map)
 endif
 
 # type = 0x52 - PSP Bootloader Userspace Application (verstage)
@@ -225,7 +224,8 @@ $(obj)/amdfw.rom:	$(call strip_quotes, $(PSP_BIOSBIN_FILE)) \
 			$$(PSP_APCB_FILES) \
 			$(DEP_FILES) \
 			$(AMDFWTOOL) \
-			$(obj)/fmap_config.h
+			$(obj)/fmap_config.h \
+			$(objcbfs)/bootblock.elf # this target also creates the .map file
 	$(if $(PSP_APCB_FILES), ,$(error APCB_SOURCES is not set))
 	rm -f $@
 	@printf "    AMDFWTOOL  $(subst $(obj)/,,$(@))\n"

src/soc/amd/picasso/include/soc/gpio.h

@@ -9,6 +9,9 @@
 #ifndef __ACPI__
 #include <soc/iomap.h>
 #include <amdblocks/gpio_banks.h>
+#endif /* !__ACPI__ */
+
+#include <amdblocks/gpio_defs.h>
 
 /* The following sections describe only the GPIOs defined for this SOC */
 
@@ -296,5 +299,4 @@
 
 #define GPIO_2_EVENT GEVENT_8
 
-#endif /* __ACPI__ */
 #endif /* AMD_PICASSO_GPIO_H */

src/soc/amd/picasso/include/soc/romstage.h

+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_ROMSTAGE_H_
+#define _SOC_ROMSTAGE_H_
+
+#include <fsp/api.h>
+
+void mainboard_updm_update(FSP_M_CONFIG *mcfg);
+
+#endif /* _SOC_ROMSTAGE_H_ */

src/soc/amd/picasso/romstage.c

@@ -16,10 +16,12 @@
 #include <elog.h>
 #include <soc/acpi.h>
 #include <soc/pci_devs.h>
+#include <soc/romstage.h>
 #include <types.h>
 #include "chip.h"
 #include <fsp/api.h>
 
+void __weak mainboard_updm_update(FSP_M_CONFIG *mupd) {}
 static struct chipset_power_state chipset_state;
 
 static void fill_chipset_state(void)
@@ -139,6 +141,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 	mcfg->telemetry_vddcr_soc_offset = config->telemetry_vddcr_soc_offset;
 	mcfg->hd_audio_enable = devtree_hda_dev_enabled();
 	mcfg->sata_enable = devtree_sata_dev_enabled();
+
+	mainboard_updm_update(mcfg);
 }
 
 asmlinkage void car_stage_entry(void)