Commits (26)
-
Nico Huber authored
Currently, if everything worked fine, `$fail` will be unset, leading to the following `if` statement: if [ -eq 1 ] Resulting in the error message: /bin/sh: line 9: [: -eq: unary operator expected Fix this by removing the whole `if`, we can just use `exit`. Change-Id: I1bc7508d2a45a2bec07ef46b9c5d9d0b740fbc74 Signed-off-by:Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51324Tested-by:
build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by:
Angel Pons <th3fanbus@gmail.com> Reviewed-by:
Furquan Shaikh <furquan@google.com>
21666e46 -
Nico Huber authored
Perform some cosmetical changes: * Override the first prerequisite so we can use `$<`. * Add/remove whitspace to align things (recipe needs to be indented by a single tab only). * We can use shell variables inside double quotes. To make the end of the variable name clear, use braces, e.g. "${x}". NB. Most of the double quotes are unnecessary. They only change the way the script would be failing in case of spurious whitespace. * Break some lines doing multiple things at once. * To reduce remaining clutter, put reading numbers into a shell function. And functional changes: * No need to spawn `cat`, the shell can redirect input as well as output (using `<`). * To read a number from the `fmap_config.h`, we spawned 4 processes where a single one can achieve the same. With one exception: GNU awk refuses to parse hex numbers by default. Luckily, it turned out that we don't need intermediate decimal numbers: Shells can do arithmetic with hex values as well. Change-Id: Ia7bfba0d7864fc091ee6003e09b705fd7254e99b Signed-off-by:de85f5ce -
Furquan Shaikh authored
Currently, `check-fmap-16mib-crossing` compares the offset and end of each SPI flash region to 16MiB to ensure that no region is placed across this 16MiB boundary from the start of SPI flash. What really needs to be checked is that the region isn't placed across the 16MiB boundary from the end of BIOS region. Thus, current check works only if the SPI flash is 32MiB under the assumption that the BIOS region is mapped at the top of SPI flash. However, this check will not work if a flash part greater than 32MiB is used. This change replaces the hardcoded boundary value of 16MiB with a value calculated by subtracting 16MiB from the SPI flash size (if it is greater than 16MiB). This calculated value is used as the boundary that no region defined in the flashmap should be placed across. The assumption here is that BIOS region is always placed at the top of SPI flash. Hence, the standard decode window would be from end_of_flash - 16M to end_of_flash (because end_of_flash = end_of_bios_region). Currently, there is no consistency in the name used for BIOS region in flashmap layout for boards in coreboot. But all Intel-based boards (except APL and GLK) place BIOS region at the end of SPI flash. Since APL and GLK do not support the extended window, this check does not matter for these platforms. Change-Id: Icff83e5bffacfd443c1c3fbc101675c4a6f75e24 Signed-off-by:
d09d8de7 -
Raul E Rangel authored
Needed to get the _SX ASL methods. Signed-off-by:
Raul E Rangel <rrangel@chromium.org> Signed-off-by:
Felix Held <felix-coreboot@felixheld.de> Change-Id: I6323ba413a21d9d867727dbb28340e6df807c86a Reviewed-on: https://review.coreboot.org/c/coreboot/+/51303Tested-by:
c14bbc9c -
Raul E Rangel authored
Since not all mainboards based on the Cezanne SoC have to support ACPI resume, select this option in the mainboard's Kconfig and not in the SoC's Kconfig. Signed-off-by:
88dbfa96 -
Mathew King authored
Add the option to build guybrush firmware with support for EM100. This will assist in bringup of the new board. BUG=b:180723776 TEST=builds Signed-off-by:
Mathew King <mathewk@chromium.org> Change-Id: I2246d2952f341cd8fff8fd486cf989cdb7929411 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51071Reviewed-by:
Martin Roth <martinroth@google.com> Tested-by:
60954722 -
Martin Roth authored
This enables the standard library method of adding SPDs to CBFS. BUG=b:178715165 TEST=Build Signed-off-by:
Martin Roth <martin@coreboot.org> Change-Id: I2ec94fd866409e1dfa5cb65f6960ea07cbe22f2a Reviewed-on: https://review.coreboot.org/c/coreboot/+/51022Reviewed-by:
de89e950 -
Alexander Couzens authored
Without the boot template, u-root doesn't include any boot commands. Booting other OS is impossible. Signed-off-by:
Alexander Couzens <lynxis@fe80.eu> Change-Id: I7d0742d115715eb40e293e2a8711d1ff20d8970a Reviewed-on: https://review.coreboot.org/c/coreboot/+/51331Reviewed-by:
Arthur Heymans <arthur@aheymans.xyz> Reviewed-by:
ron minnich <rminnich@gmail.com> Tested-by:
6e4e6207 -
Felix Held authored
The bank names were copied over from Stoneyridge, but they don't match for Picasso. TEST=Checked the Picasso PPR. Signed-off-by:
Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by:
108a4763 -
Felix Held authored
The Picasso APUs advertise 23 MCA banks in the lower byte of the IA32_MCG_CAP MSR, which is more than the 7 core MCA banks. Signed-off-by:
4cd9ac0a -
Nico Huber authored
The current values are actually for 32MiB and result in a brick if used with a 16MiB chip because of the invalid bios region. Change-Id: I08337394ce0d6e31e5c03cda2bfb3b9f0282f2c3 Signed-off-by:
Evgeny Zinoviev <me@ch1p.io> Reviewed-by:
Paul Menzel <paulepanter@users.sourceforge.net> Tested-by:
3b14a5f9 -
Nikolai Vyssotski authored
To use this, Enable "CONFIG_RUN_FSP_GOP" in the platform's Kconfig. BUG=b:171234996 TEST=Boot Majolica with GOP graphics Change-Id: Ic9401cc93ee50fb7dbd84fe26ef24306a1673f58 Signed-off-by:
Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51422Tested-by:
0671d736 -
Mathew King authored
BUG=b:181690884 TEST=builds Signed-off-by:
095bdeca -
Arthur Heymans authored
Let the linker do its job. This fixes building with !CONFIG_PCIEXP_HOTPLUG on some platforms. Change-Id: I46560722dcb5f1d902709e40b714ef092515b164 Signed-off-by:
24837e75 -
Mathew King authored
BUG=b:180531661 TEST=builds Signed-off-by:
d2c5b0e9 -
Martin Roth authored
Updating from commit id 4fdfa1c: 2021-03-05 13:10:22 -0600 - (mb/amd/majolica: Update to use proper APCBs built for Majolica) to commit id fc2d4e2: 2021-03-12 10:31:48 -0700 - (mb/google/guybrush: Add initial APCB) This brings in 1 new commit. Signed-off-by:
c381b194 -
Martin Roth authored
Updating from commit id 3b1a734: 2021-03-02 11:51:18 -0700 - (picasso: Update FSP to build 0x26) to commit id 3a9d7cd: 2021-03-03 15:37:08 -0700 - (picasso: Update Dali SMU firmware) This brings in 1 new commits. Signed-off-by:
50c667de -
Yidi Lin authored
Move the initialization from bootblock to romstage for following reasons: - Follow MT8183 initialization sequence. - PMIC and RTC functions are only called after verstage. - Reduce bootblock size. - PMIC initialization setting is complex and may need to be changed by an RW firmware update. TEST=boot to kernel successfully Change-Id: I3e4c3f918639590ffc73076450235771d06aae91 Signed-off-by:
Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51409Tested-by:
Xi Chen <xixi.chen@mediatek.com> Reviewed-by:
Hung-Te Lin <hungte@chromium.org>
2fcbebbb -
Hung-Te Lin authored
The SKU ID for Asurada should come from AP ADC channel 5 and 6. BUG=None TEST=make; boots on asurada Change-Id: I6a00c555f20aca4cd7f8bcee46ee81c17ef6ca3c Signed-off-by:
Yu-Ping Wu <yupingso@google.com>
a79d6e76 -
Nina Wu authored
MT8192 devapc supports remapping domains. There may be different domain bit for different subsys. For example, domain bit in INFRA is 4-bit, while in MMSYS, domain bit is 2-bit. For INFRA master to access MM registers, the domain bit will change from 4 to 2 and need to be remapped. In this patch we have remapped: 1. TINYSYS (3-bit to 4-bit) - domain 3 to domain 3 - others to domain 15 2. MMSYS slave (4-bit to 2-bit) - domain X to domain X, for X = 0 ~ 3 - others to domain 0 Change-Id: Id10a4c0bdf141cc76a386159896c861d0dc302aa Signed-off-by:
Nina Wu <nina-cm.wu@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49790Tested-by:
31f914c5 -
Kevin Chiu authored
This reverts commit 87a1bd69. Reason for revert: skin temperature is overheating due to boost time is too long BUG=b:175364713 TEST=1. emerge-zork coreboot 2. run balance performance and skin temperature test => pass Signed-off-by:
Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I31db06f4bcb986398e7bd2ac2858ffbedb257e2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/51391Tested-by:
Kangheui Won <khwon@chromium.org> Reviewed-by:
Daniel Kurtz <djkurtz@google.com> Reviewed-by:
Edward O'Callaghan <quasisec@chromium.org>
ae5ab182 -
Angel Pons authored
The `HPET_ADDRESS` Kconfig option has the same value. Use it instead. Change-Id: I268e949d4396aa20e38f719b36cc4e6226efe082 Signed-off-by:
0b39379c -
Angel Pons authored
Done for consistency with other platforms. This also drops redundant S3 resume logging, as `southbridge_detect_s3_resume` already prints it. Tested on Asrock B85M Pro4, still boots and still resumes from S3. Change-Id: Id96c5aedad80702ebf343dd0a351fbd4e7b1c6c1 Signed-off-by:
30931f5a -
Zanxi Chen authored
Add touchpad into devicetree for blipper. BUG=b:172787208 BRANCH=dedede TEST=built blipper firmware and verified touchpad function the kernel log: found RMI device, manufacturer: Synaptics Change-Id: I2c9b61ba9d282f994e2f756bafe4af1091d4d617 Signed-off-by:
Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51188Reviewed-by:
Karthik Ramasubramanian <kramasub@google.com> Reviewed-by:
535d6d8c -
Tim Wawrzynczak authored
The _DSD is generated at runtime using the Intel common USB4 driver, therefore remove it from the ASL files. BUG=b:182522802, b:182478306 TEST=boot into latest kernel, no thunderbolt driver errors seen Signed-off-by:
Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I77dc283aeb5f52191255137e941487cf68cb7970 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51453Reviewed-by:
EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by:
b1047807 -
Tim Wawrzynczak authored
The _DSD is generated at runtime using the Intel common pcie driver, therefore remove it from the ASL files. BUG=b:182522802, b:182478306 TEST=boot into latest kernel, no thunderbolt driver errors seen Signed-off-by:
99ab1fd1
Showing