src/mainboard/google/dedede/variants/boten/overridetree.cb

@@ -216,14 +216,14 @@ chip soc/intel/jasperlake
 				register "reg_gnrl_ctrl0" = "0x0a"
 				register "reg_gnrl_ctrl1" = "0x22"
 				register "reg_afe_ctrl0" = "0x20"
-				register "reg_afe_ctrl3" = "0x00"
+				register "reg_afe_ctrl3" = "0x01"
 				register "reg_afe_ctrl4" = "0x47"
 				register "reg_afe_ctrl6" = "0x00"
 				register "reg_afe_ctrl7" = "0x47"
 				register "reg_afe_ctrl8" = "0x12"
-				register "reg_afe_ctrl9" = "0x08"
+				register "reg_afe_ctrl9" = "0x0f"
 				register "reg_afe_ph0" = "0x37"
-				register "reg_afe_ph1" = "0x10"
+				register "reg_afe_ph1" = "0x29"
 				register "reg_afe_ph2" = "0x1f"
 				register "reg_afe_ph3" = "0x3d"
 				register "reg_prox_ctrl0" = "0x0b"
@@ -232,7 +232,7 @@ chip soc/intel/jasperlake
 				register "reg_prox_ctrl3" = "0x20"
 				register "reg_prox_ctrl4" = "0x0c"
 				register "reg_prox_ctrl5" = "0x00"
-				register "reg_prox_ctrl6" = "0x1c"
+				register "reg_prox_ctrl6" = "0x2d"
 				register "reg_prox_ctrl7" = "0xc0"
 				register "reg_adv_ctrl0" = "0x00"
 				register "reg_adv_ctrl1" = "0x00"
@@ -252,13 +252,13 @@ chip soc/intel/jasperlake
 				register "reg_adv_ctrl15" = "0x0c"
 				register "reg_adv_ctrl16" = "0x04"
 				register "reg_adv_ctrl17" = "0x70"
-				register "reg_adv_ctrl18" = "0x20"
+				register "reg_adv_ctrl18" = "0x40"
 				register "reg_adv_ctrl19" = "0x00"
 				register "reg_adv_ctrl20" = "0x00"
 				register "reg_irq_msk" = "0x6f"
 				register "reg_irq_cfg0" = "0x00"
 				register "reg_irq_cfg1" = "0x80"
-				register "reg_irq_cfg2" = "0x01"
+				register "reg_irq_cfg2" = "0x00"
 				device i2c 28 on end
 			end
 		end # I2C 5

src/soc/amd/cezanne/include/soc/smu.h

@@ -3,13 +3,10 @@
 #ifndef AMD_CEZANNE_SMU_H
 #define AMD_CEZANNE_SMU_H
 
-/*
- * SMU mailbox register offsets in indirect address space accessed by an index/data pair in
- * D0F00 config space.
- */
-#define REG_ADDR_MESG_ID	0x3b10528
-#define REG_ADDR_MESG_RESP	0x3b10564
-#define REG_ADDR_MESG_ARGS_BASE	0x3b10998
+/* SMU mailbox register offsets in SMN */
+#define SMN_SMU_MESG_ID		0x3b10528
+#define SMN_SMU_MESG_RESP	0x3b10564
+#define SMN_SMU_MESG_ARGS_BASE	0x3b10998
 
 #define SMU_NUM_ARGS		6
 

src/soc/amd/common/block/include/amdblocks/smn.h

+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_BLOCK_SMN_H
+#define AMD_BLOCK_SMN_H
+
+#include <types.h>
+
+uint32_t smn_read32(uint32_t reg);
+void smn_write32(uint32_t reg, uint32_t val);
+
+#endif /* AMD_BLOCK_SMN_H */

src/soc/amd/common/block/include/amdblocks/smu.h

@@ -6,12 +6,8 @@
 #include <types.h>
 #include <soc/smu.h> /* SoC-dependent definitions for SMU access */
 
-/* SMU registers accessed indirectly using an index/data pair in D0F00 config space */
-#define SMU_INDEX_ADDR		0xb8 /* 32 bit */
-#define SMU_DATA_ADDR		0xbc /* 32 bit */
-
 /* Arguments indexed locations are contiguous; the number is SoC-dependent */
-#define REG_ADDR_MESG_ARG(x)	(REG_ADDR_MESG_ARGS_BASE + ((x) * sizeof(uint32_t)))
+#define SMN_SMU_MESG_ARG(x)	(SMN_SMU_MESG_ARGS_BASE + ((x) * sizeof(uint32_t)))
 
 struct smu_payload {
 	uint32_t msg[SMU_NUM_ARGS];

src/soc/amd/common/block/smn/Kconfig

+config SOC_AMD_COMMON_BLOCK_SMN
+	bool
+	help
+	  Select this option to add functions to access the SMN register space to the build.

src/soc/amd/common/block/smn/Makefile.inc

+ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_SMN),y)
+
+bootblock-y += smn.c
+romstage-y += smn.c
+ramstage-y += smn.c
+smm-y += smn.c
+
+endif # CONFIG_SOC_AMD_COMMON_BLOCK_SMN

src/soc/amd/common/block/smn/smn.c

+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/smn.h>
+#include <device/pci_ops.h>
+#include <soc/pci_devs.h>
+#include <types.h>
+
+/* SMN registers accessed indirectly using an index/data pair in D0F00 config space */
+#define SMN_INDEX_ADDR		0xb8 /* 32 bit */
+#define SMN_DATA_ADDR		0xbc /* 32 bit */
+
+uint32_t smn_read32(uint32_t reg)
+{
+	pci_write_config32(SOC_GNB_DEV, SMN_INDEX_ADDR, reg);
+	return pci_read_config32(SOC_GNB_DEV, SMN_DATA_ADDR);
+}
+
+void smn_write32(uint32_t reg, uint32_t val)
+{
+	pci_write_config32(SOC_GNB_DEV, SMN_INDEX_ADDR, reg);
+	pci_write_config32(SOC_GNB_DEV, SMN_DATA_ADDR, val);
+}

src/soc/amd/common/block/smu/Kconfig

 config SOC_AMD_COMMON_BLOCK_SMU
 	bool
+	select SOC_AMD_COMMON_BLOCK_SMN
 	help
 	  Select this option to add functions to communicate with the SMU to the build.

src/soc/amd/common/block/smu/smu.c

@@ -2,24 +2,11 @@
 
 #include <timer.h>
 #include <console/console.h>
-#include <device/pci_ops.h>
+#include <amdblocks/smn.h>
 #include <amdblocks/smu.h>
-#include <soc/pci_devs.h>
 #include <soc/smu.h>
 #include <types.h>
 
-static uint32_t smu_read32(uint32_t reg)
-{
-	pci_write_config32(SOC_GNB_DEV, SMU_INDEX_ADDR, reg);
-	return pci_read_config32(SOC_GNB_DEV, SMU_DATA_ADDR);
-}
-
-static void smu_write32(uint32_t reg, uint32_t val)
-{
-	pci_write_config32(SOC_GNB_DEV, SMU_INDEX_ADDR, reg);
-	pci_write_config32(SOC_GNB_DEV, SMU_DATA_ADDR, val);
-}
-
 #define SMU_MESG_RESP_TIMEOUT	0x00
 #define SMU_MESG_RESP_OK	0x01
 
@@ -33,7 +20,7 @@ static int32_t smu_poll_response(bool print_command_duration)
 	stopwatch_init_msecs_expire(&sw, timeout_ms);
 
 	do {
-		result = smu_read32(REG_ADDR_MESG_RESP);
+		result = smn_read32(SMN_SMU_MESG_RESP);
 		if (result) {
 			if (print_command_duration)
 				printk(BIOS_SPEW, "SMU command consumed %ld usecs\n",
@@ -59,14 +46,14 @@ enum cb_err send_smu_message(enum smu_message_id message_id, struct smu_payload
 		return CB_ERR;
 
 	/* clear response register */
-	smu_write32(REG_ADDR_MESG_RESP, 0);
+	smn_write32(SMN_SMU_MESG_RESP, 0);
 
 	/* populate arguments */
 	for (i = 0 ; i < SMU_NUM_ARGS ; i++)
-		smu_write32(REG_ADDR_MESG_ARG(i), arg->msg[i]);
+		smn_write32(SMN_SMU_MESG_ARG(i), arg->msg[i]);
 
 	/* send message to SMU */
-	smu_write32(REG_ADDR_MESG_ID, message_id);
+	smn_write32(SMN_SMU_MESG_ID, message_id);
 
 	/* wait until SMU has processed the message and check if it was successful */
 	if (smu_poll_response(true) != SMU_MESG_RESP_OK)
@@ -74,7 +61,7 @@ enum cb_err send_smu_message(enum smu_message_id message_id, struct smu_payload
 
 	/* copy returned values */
 	for (i = 0 ; i < SMU_NUM_ARGS ; i++)
-		arg->msg[i] = smu_read32(REG_ADDR_MESG_ARG(i));
+		arg->msg[i] = smn_read32(SMN_SMU_MESG_ARG(i));
 
 	return CB_SUCCESS;
 }

src/soc/amd/picasso/include/soc/smu.h

@@ -3,13 +3,10 @@
 #ifndef AMD_PICASSO_SMU_H
 #define AMD_PICASSO_SMU_H
 
-/*
- * SMU mailbox register offsets in indirect address space accessed by an index/data pair in
- * D0F00 config space.
- */
-#define REG_ADDR_MESG_ID	0x3b10528
-#define REG_ADDR_MESG_RESP	0x3b10564
-#define REG_ADDR_MESG_ARGS_BASE	0x3b10998
+/* SMU mailbox register offsets in SMN */
+#define SMN_SMU_MESG_ID		0x3b10528
+#define SMN_SMU_MESG_RESP	0x3b10564
+#define SMN_SMU_MESG_ARGS_BASE	0x3b10998
 
 #define SMU_NUM_ARGS		6