src/mainboard/facebook/watson/Kconfig

@@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select HAVE_ACPI_TABLES
 	select HAVE_OPTION_TABLE
 	select INTEGRATED_UART
+	select IPMI_KCS if BOARD_FACEBOOK_WATSON_V2
 	select SERIRQ_CONTINUOUS_MODE
 	select MAINBOARD_USES_IFD_GBE_REGION
 	select MAINBOARD_HAS_LPC_TPM
@@ -36,6 +37,10 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "Watson"
 
+config DEVICETREE
+	string
+	default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
+
 config IRQ_SLOT_COUNT
 	int
 	default 18
@@ -46,6 +51,7 @@ config CBFS_SIZE
 
 config VARIANT_DIR
 	string
+	default "watson" if BOARD_FACEBOOK_WATSON
 	default "watson_v2" if BOARD_FACEBOOK_WATSON_V2
 
 config VBOOT_FWID_MODEL

src/mainboard/facebook/watson/Makefile.inc

@@ -15,4 +15,5 @@
 
 ramstage-y += irqroute.c
 
+subdirs-y += variants/$(VARIANT_DIR)
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include

src/mainboard/facebook/watson/include/variants.h

@@ -21,5 +21,6 @@
 #include <soc/romstage.h>
 
 void variant_romstage_fsp_init_params(UPD_DATA_REGION *UpdData);
+void variant_early_mainboard_romstage_entry(void);
 
 #endif /* BASEBOARD_VARIANTS_H */

src/mainboard/facebook/watson/romstage.c

@@ -25,7 +25,7 @@
  */
 void early_mainboard_romstage_entry(void)
 {
-
+	variant_early_mainboard_romstage_entry();
 }
 
 /**
@@ -52,3 +52,8 @@ __weak void variant_romstage_fsp_init_params(UPD_DATA_REGION *UpdData)
 {
 
 }
+
+__weak void variant_early_mainboard_romstage_entry(void)
+{
+
+}

src/mainboard/facebook/watson/variants/watson_v2/devicetree.cb

+chip soc/intel/fsp_broadwell_de
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+	device domain 0 on
+		device pci 00.0 on end # SoC router
+		device pci 14.0 on end # xHCI Controller
+		device pci 19.0 on end # Gigabit LAN Controller
+		device pci 1d.0 on end # EHCI Controller
+		device pci 1f.0 on # LPC Bridge
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+			chip drivers/ipmi
+				device pnp ca2.0 on end
+				register "bmc_i2c_address" = "0x20"
+			end
+		end
+		device pci 1f.2 on end # SATA Controller
+		device pci 1f.3 on end # SMBus Controller
+		device pci 1f.5 on end # SATA Controller
+	end
+end

src/mainboard/facebook/watson/variants/watson_v2/romstage.c

@@ -15,6 +15,9 @@
  * GNU General Public License for more details.
  */
 
+#include <device/pci_ops.h>
+#include <soc/lpc.h>
+#include <soc/pci_devs.h>
 #include <soc/romstage.h>
 #include <variants.h>
 
@@ -46,3 +49,12 @@ void variant_romstage_fsp_init_params(UPD_DATA_REGION *UpdData)
 	UpdData->HotPlug_PchPciPort7 = 1;
 	UpdData->HotPlug_PchPciPort8 = 1;
 }
+
+void variant_early_mainboard_romstage_entry(void)
+{
+	// Enable LPC IO ports 0xca2, 0xca8 for IPMI
+	pci_write_config32(PCH_DEV_LPC, LPC_GEN2_DEC,
+		(0 << 16) | ALIGN_DOWN(0xca2, 4) | 1);
+	pci_write_config32(PCH_DEV_LPC, LPC_GEN3_DEC,
+		(0 << 16) | ALIGN_DOWN(0xca8, 4) | 1);
+}

src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h

@@ -56,6 +56,7 @@
 #define LPC_DEV			31
 #define LPC_FUNC		0
 #define PCH_DEVFN_LPC		PCI_DEVFN(LPC_DEV, LPC_FUNC)
+#define PCH_DEV_LPC		PCI_DEV(BUS0, LPC_DEV, LPC_FUNC)
 
 #define SATA_DEV		31
 #define SATA_FUNC		2