src/cpu/intel/microcode/microcode.c

@@ -117,18 +117,15 @@ uint32_t get_microcode_checksum(const void *microcode)
 	return ((struct microcode *)microcode)->cksum;
 }
 
-const void *intel_microcode_find(void)
+static const void *find_cbfs_microcode(void)
 {
-	static const struct microcode *ucode_updates;
+	const struct microcode *ucode_updates;
 	size_t microcode_len;
 	u32 eax;
 	u32 pf, rev, sig, update_size;
 	msr_t msr;
 	struct cpuinfo_x86 c;
 
-	if (ucode_updates)
-		return ucode_updates;
-
 	ucode_updates = cbfs_map(MICROCODE_CBFS_FILE, &microcode_len);
 	if (ucode_updates == NULL)
 		return NULL;
@@ -170,11 +167,28 @@ const void *intel_microcode_find(void)
 		microcode_len -= update_size;
 	}
 
-	ucode_updates = NULL;
-
 	return NULL;
 }
 
+const void *intel_microcode_find(void)
+{
+	static bool microcode_checked;
+	static const void *ucode_update;
+
+	if (microcode_checked)
+		return ucode_update;
+
+	/*
+	 * Since this function caches the found microcode (NULL or a valid
+	 * microcode pointer), it is expected to be run from BSP before starting
+	 * any other APs. This sequence is not multithread safe otherwise.
+	 */
+	ucode_update = find_cbfs_microcode();
+	microcode_checked = true;
+
+	return ucode_update;
+}
+
 void intel_update_microcode_from_cbfs(void)
 {
 	const void *patch = intel_microcode_find();

src/include/cpu/intel/microcode.h

@@ -7,7 +7,11 @@
 void intel_update_microcode_from_cbfs(void);
 /* Find a microcode that matches the revision and platform family returning
  * NULL if none found. The found microcode is cached for faster access on
- * subsequent calls of this function. */
+ * subsequent calls of this function.
+ *
+ * Since this function caches the found microcode (NULL or a valid microcode
+ * pointer), it is expected to be run from BSP before starting any other APs.
+ * It is not multithread safe otherwise. */
 const void *intel_microcode_find(void);
 
 /* It is up to the caller to determine if parallel loading is possible as

src/mainboard/google/dedede/variants/boten/overridetree.cb

@@ -51,6 +51,12 @@ chip soc/intel/jasperlake
 		},
 		.i2c[5] = {
 			.speed = I2C_SPEED_FAST,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST,
+				.scl_lcnt = 190,
+				.scl_hcnt = 100,
+				.sda_hold = 40,
+			}
 		},
 	}"
 
@@ -152,8 +158,12 @@ chip soc/intel/jasperlake
 				register "generic.probed" = "1"
 				register "generic.reset_gpio" =
 							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)"
-				register "generic.reset_delay_ms" = "120"
+				register "generic.reset_delay_ms" = "180"
 				register "generic.reset_off_delay_ms" = "3"
+				register "generic.stop_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)"
+				register "generic.stop_delay_ms" = "20"
+				register "generic.stop_off_delay_ms" = "2"
 				register "generic.enable_gpio" =
 							"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)"
 				register "generic.enable_delay_ms" = "12"