src/cpu/x86/mp_init.c

@@ -992,6 +992,28 @@ int mp_run_on_aps(void (*func)(void *), void *arg, int logical_cpu_num,
 	return run_ap_work(&lcb, expire_us);
 }
 
+int mp_run_on_all_aps(void (*func)(void *), void *arg, long expire_us, bool run_parallel)
+{
+	int ap_index, bsp_index;
+
+	if (run_parallel)
+		return mp_run_on_aps(func, arg, 0, expire_us);
+
+	bsp_index = cpu_index();
+
+	const int total_threads = global_num_aps + 1; /* +1 for BSP */
+
+	for (ap_index = 0; ap_index < total_threads; ap_index++) {
+		/* skip if BSP */
+		if (ap_index == bsp_index)
+			continue;
+		if (mp_run_on_aps(func, arg, ap_index, expire_us))
+			return CB_ERR;
+	}
+
+	return CB_SUCCESS;
+}
+
 int mp_run_on_all_cpus(void (*func)(void *), void *arg)
 {
 	/* Run on BSP first. */

src/drivers/intel/fsp2_0/include/fsp/ppi/mp_service_ppi.h

@@ -24,7 +24,7 @@ efi_return_status_t mp_get_processor_info(efi_uintn_t processor_number,
 
 /* executes a caller provided function on all enabled APs */
 efi_return_status_t mp_startup_all_aps(efi_ap_procedure procedure,
-	efi_uintn_t timeout_usec, void *argument);
+	bool run_serial, efi_uintn_t timeout_usec, void *argument);
 
 /* executes a caller provided function on all enabled APs + BSP */
 efi_return_status_t mp_startup_all_cpus(efi_ap_procedure procedure,

src/drivers/intel/fsp2_0/ppi/mp_service1.c

@@ -23,10 +23,10 @@ static efi_return_status_t mps1_get_processor_info(const
 
 static efi_return_status_t mps1_startup_all_aps(const
 	efi_pei_services **ignored1, efi_pei_mp_services_ppi *ignored2,
-	efi_ap_procedure procedure, efi_boolean_t ignored3,
+	efi_ap_procedure procedure, efi_boolean_t run_serial,
 	efi_uintn_t timeout_usec, void *argument)
 {
-	return mp_startup_all_aps(procedure, timeout_usec, argument);
+	return mp_startup_all_aps(procedure, run_serial, timeout_usec, argument);
 }
 
 static efi_return_status_t mps1_startup_this_ap(const

src/drivers/intel/fsp2_0/ppi/mp_service2.c

@@ -24,10 +24,10 @@ static efi_return_status_t mps2_get_processor_info(
 
 static efi_return_status_t mps2_startup_all_aps(
 	efi_pei_mp_services_ppi *ignored1,
-	efi_ap_procedure procedure, efi_boolean_t ignored2,
+	efi_ap_procedure procedure, efi_boolean_t run_serial,
 	efi_uintn_t timeout_usec, void *argument)
 {
-	return mp_startup_all_aps(procedure, timeout_usec, argument);
+	return mp_startup_all_aps(procedure, run_serial, timeout_usec, argument);
 }
 
 static efi_return_status_t mps2_startup_all_cpus(

src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c

@@ -64,7 +64,7 @@ efi_return_status_t mp_get_processor_info(efi_uintn_t processor_number,
 }
 
 efi_return_status_t mp_startup_all_aps(efi_ap_procedure procedure,
-	efi_uintn_t timeout_usec, void *argument)
+	bool run_serial, efi_uintn_t timeout_usec, void *argument)
 {
 	if (cpu_index() < 0)
 		return FSP_DEVICE_ERROR;
@@ -72,8 +72,7 @@ efi_return_status_t mp_startup_all_aps(efi_ap_procedure procedure,
 	if (procedure == NULL)
 		return FSP_INVALID_PARAMETER;
 
-	if (mp_run_on_aps((void *)procedure, argument,
-			MP_RUN_ON_ALL_CPUS, timeout_usec)) {
+	if (mp_run_on_all_aps((void *)procedure, argument, timeout_usec, !run_serial)) {
 		printk(BIOS_DEBUG, "%s: Exit with Failure\n", __func__);
 		return FSP_NOT_STARTED;
 	}

src/include/cpu/x86/mp.h

@@ -125,6 +125,12 @@ enum {
 int mp_run_on_aps(void (*func)(void *), void *arg, int logical_cpu_num,
 		long expire_us);
 
+/*
+ * Runs func on all APs excluding BSP, with a provision to run calls in parallel
+ * or serially per AP.
+ */
+int mp_run_on_all_aps(void (*func)(void *), void *arg, long expire_us, bool run_parallel);
+
 /* Like mp_run_on_aps() but also runs func on BSP. */
 int mp_run_on_all_cpus(void (*func)(void *), void *arg);
 

src/mainboard/google/mancomb/Kconfig

@@ -7,8 +7,20 @@ if BOARD_GOOGLE_BASEBOARD_MANCOMB
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select AMD_SOC_CONSOLE_UART
 	select BOARD_ROMSIZE_KB_16384
+	select MAINBOARD_HAS_CHROMEOS
 	select SOC_AMD_CEZANNE
+	select SOC_AMD_COMMON_BLOCK_USE_ESPI
+
+config CHROMEOS
+	select EC_GOOGLE_CHROMEEC
+	select EC_GOOGLE_CHROMEEC_ESPI
+	select EC_GOOGLE_CHROMEEC_SWITCHES
+
+config VBOOT
+	select VBOOT_SEPARATE_VERSTAGE
+	select VBOOT_STARTS_IN_BOOTBLOCK
 
 config FMDFILE
 	string
@@ -28,10 +40,18 @@ config AMD_FWM_POSITION_INDEX
 	help
 	  TODO: might need to be adapted for better placement of files in cbfs
 
+config VARIANT_DIR
+	string
+	default "mancomb" if BOARD_GOOGLE_MANCOMB
+
 config DEVICETREE
 	string
 	default "variants/baseboard/devicetree.cb"
 
+config OVERRIDE_DEVICETREE
+	string
+	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
 config MAINBOARD_FAMILY
 	string
 	default "Google_Mancomb"

src/mainboard/google/mancomb/Makefile.inc

@@ -3,6 +3,10 @@
 bootblock-y += bootblock.c
 
 ramstage-y += mainboard.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 
 subdirs-y += variants/baseboard
+subdirs-y += variants/$(VARIANT_DIR)
+
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include

src/mainboard/google/mancomb/bootblock.c

@@ -5,5 +5,8 @@
 
 void bootblock_mainboard_early_init(void)
 {
-	/* TODO: Perform mainboard initialization */
+	size_t num_gpios;
+	const struct soc_amd_gpio *gpios;
+	gpios = variant_bootblock_gpio_table(&num_gpios);
+	program_gpios(gpios, num_gpios);
 }

src/mainboard/google/mancomb/chromeos.c

+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <boot/coreboot_tables.h>
+#include <gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+	struct lb_gpio chromeos_gpios[] = {
+		{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
+		{-1, ACTIVE_HIGH, 0, "power"},
+	};
+	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+}
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AL(CROS_WP_GPIO, GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}

src/mainboard/google/mancomb/mainboard.c

 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
+#include <baseboard/variants.h>
 #include <device/device.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+static void mainboard_configure_gpios(void)
+{
+	size_t base_num_gpios, override_num_gpios;
+	const struct soc_amd_gpio *base_gpios, *override_gpios;
+	base_gpios = variant_base_gpio_table(&base_num_gpios);
+	override_gpios = variant_override_gpio_table(&override_num_gpios);
+	gpio_configure_pads_with_override(base_gpios, base_num_gpios, override_gpios,
+					  override_num_gpios);
+}
 
 static void mainboard_init(void *chip_info)
 {
-	/* TODO: Perform mainboard initialization */
+	mainboard_configure_gpios();
 }
 
 static void mainboard_enable(struct device *dev)
 {
-	/* TODO: Enable mainboard */
+	printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+	dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
 }
 
 struct chip_operations mainboard_ops = {

src/mainboard/google/mancomb/variants/baseboard/Makefile.inc

+bootblock-y += gpio.c
+
+ramstage-y += gpio.c

src/mainboard/google/mancomb/variants/baseboard/devicetree.cb

 # SPDX-License-Identifier: GPL-2.0-or-later
 chip soc/amd/cezanne
+
+	# eSPI Configuration
+	register "common_config.espi_config" = "{
+		.std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X60_0X64_EN,
+		.generic_io_range[0] = {
+			.base = 0x62,
+			/*
+			 * Only 0x62 and 0x66 are required. But, this is not supported by
+			 * standard IO decodes and there are only 4 generic I/O windows
+			 * available. Hence, open a window from 0x62-0x67.
+			 */
+			.size = 5,
+		},
+		.generic_io_range[1] = {
+			.base = 0x800,   /* EC_HOST_CMD_REGION0 */
+			.size = 256,     /* EC_HOST_CMD_REGION_SIZE * 2 */
+		},
+		.generic_io_range[2] = {
+			.base = 0x900,   /* EC_LPC_ADDR_MEMMAP */
+			.size = 255,     /* EC_MEMMAP_SIZE */
+		},
+		.generic_io_range[3] = {
+			.base = 0x200,   /* EC_LPC_ADDR_HOST_DATA */
+			.size = 8,       /* 0x200 - 0x207 */
+		},
+
+		.io_mode = ESPI_IO_MODE_QUAD,
+		.op_freq_mhz = ESPI_OP_FREQ_33_MHZ,
+		.crc_check_enable = 1,
+		.dedicated_alert_pin = 1,
+		.periph_ch_en = 1,
+		.vw_ch_en = 1,
+		.oob_ch_en = 0,
+		.flash_ch_en = 0,
+
+		.vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1) | ESPI_VW_IRQ_LEVEL_HIGH(12),
+	}"
+
 	device domain 0 on
 	end # domain
 end	# chip soc/amd/cezanne

src/mainboard/google/mancomb/variants/baseboard/gpio.c

+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+
+/* GPIO configuration in ramstage*/
+static const struct soc_amd_gpio base_gpio_table[] = {
+	/* TODO: Fill gpio configuration */
+};
+
+/* Early GPIO configuration in bootblock */
+static const struct soc_amd_gpio bootblock_gpio_table[] = {
+	/* TODO: Fill bootblock gpio configuration */
+};
+
+const struct soc_amd_gpio *__weak variant_base_gpio_table(size_t *size)
+{
+	*size = ARRAY_SIZE(base_gpio_table);
+	return base_gpio_table;
+}
+const struct soc_amd_gpio *__weak variant_override_gpio_table(size_t *size)
+{
+	*size = 0;
+	return NULL;
+}
+
+const struct soc_amd_gpio *__weak variant_bootblock_gpio_table(size_t *size)
+{
+	*size = ARRAY_SIZE(bootblock_gpio_table);
+	return bootblock_gpio_table;
+}

src/mainboard/google/mancomb/variants/baseboard/include/baseboard/gpio.h

@@ -3,4 +3,7 @@
 #ifndef __BASEBOARD_GPIO_H__
 #define __BASEBOARD_GPIO_H__
 
+/* SPI Write protect */
+#define CROS_WP_GPIO GPIO_67
+
 #endif /* __BASEBOARD_GPIO_H__ */

src/mainboard/google/mancomb/variants/baseboard/include/baseboard/variants.h

@@ -3,4 +3,22 @@
 #ifndef __BASEBOARD_VARIANTS_H__
 #define __BASEBOARD_VARIANTS_H__
 
+#include <amdblocks/gpio_banks.h>
+
+/*
+ * This function provides base GPIO configuration table. It is typically provided by
+ * baseboard using a weak implementation. If GPIO configuration for a variant differs
+ * significantly from the baseboard, then the variant can also provide a strong implementation
+ * of this function.
+ */
+const struct soc_amd_gpio *variant_base_gpio_table(size_t *size);
+/*
+ * This function allows variant to override any GPIOs that are different than the base GPIO
+ * configuration provided by variant_base_gpio_table().
+ */
+const struct soc_amd_gpio *variant_override_gpio_table(size_t *size);
+
+/* This function provides GPIO init in bootblock. */
+const struct soc_amd_gpio *variant_bootblock_gpio_table(size_t *size);
+
 #endif /* __BASEBOARD_VARIANTS_H__ */

src/mainboard/google/mancomb/variants/mancomb/overridetree.cb

+chip soc/amd/cezanne
+	device domain 0 on
+	end # domain
+end # chip soc/amd/cezanne

src/soc/amd/cezanne/cpu.c

 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <amdblocks/cpu.h>
+#include <amdblocks/reset.h>
 #include <amdblocks/smm.h>
 #include <console/console.h>
 #include <cpu/amd/microcode.h>
@@ -12,7 +13,6 @@
 #include <device/device.h>
 #include <soc/cpu.h>
 #include <soc/iomap.h>
-#include <soc/reset.h>
 
 /* MP and SMM loading initialization */
 

src/soc/amd/cezanne/include/soc/reset.h

-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef AMD_CEZANNE_RESET_H
-#define AMD_CEZANNE_RESET_H
-
-void set_warm_reset_flag(void);
-int is_warm_reset(void);
-
-#endif /* AMD_CEZANNE_RESET_H */

src/soc/amd/cezanne/reset.c

@@ -3,7 +3,6 @@
 #include <arch/io.h>
 #include <cf9_reset.h>
 #include <reset.h>
-#include <soc/reset.h>
 #include <soc/southbridge.h>
 #include <amdblocks/acpimmio.h>
 #include <amdblocks/reset.h>

src/soc/amd/common/block/include/amdblocks/reset.h

@@ -9,6 +9,8 @@
 
 void do_warm_reset(void);
 void do_cold_reset(void);
+void set_warm_reset_flag(void);
+int is_warm_reset(void);
 
 static inline __noreturn void warm_reset(void)
 {

src/soc/amd/picasso/cpu.c

 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <amdblocks/cpu.h>
+#include <amdblocks/reset.h>
 #include <amdblocks/smm.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/mp.h>
@@ -12,7 +13,6 @@
 #include <device/pci_ops.h>
 #include <soc/pci_devs.h>
 #include <soc/cpu.h>
-#include <soc/reset.h>
 #include <soc/smi.h>
 #include <soc/iomap.h>
 #include <console/console.h>

src/soc/amd/picasso/include/soc/reset.h

-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef AMD_PICASSO_RESET_H
-#define AMD_PICASSO_RESET_H
-
-void set_warm_reset_flag(void);
-int is_warm_reset(void);
-
-#endif /* AMD_PICASSO_RESET_H */

src/soc/amd/picasso/mca.c

 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <amdblocks/reset.h>
 #include <cpu/x86/msr.h>
 #include <acpi/acpi.h>
 #include <soc/cpu.h>
-#include <soc/reset.h>
 #include <console/console.h>
 #include <arch/bert_storage.h>
 #include <cper.h>

src/soc/amd/picasso/reset.c

@@ -3,7 +3,6 @@
 #include <arch/io.h>
 #include <cf9_reset.h>
 #include <reset.h>
-#include <soc/reset.h>
 #include <soc/southbridge.h>
 #include <amdblocks/acpimmio.h>
 #include <amdblocks/reset.h>

src/soc/amd/stoneyridge/cpu.c

 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <amdblocks/reset.h>
 #include <amdblocks/smm.h>
 #include <cpu/amd/msr.h>
 #include <cpu/cpu.h>

src/soc/amd/stoneyridge/include/soc/northbridge.h

@@ -86,7 +86,5 @@
 void domain_enable_resources(struct device *dev);
 void domain_read_resources(struct device *dev);
 void fam15_finalize(void *chip_info);
-void set_warm_reset_flag(void);
-int is_warm_reset(void);
 
 #endif /* AMD_STONEYRIDGE_NORTHBRIDGE_H */

src/soc/amd/stoneyridge/mca.c

 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <amdblocks/reset.h>
 #include <cpu/x86/msr.h>
 #include <acpi/acpi.h>
 #include <soc/cpu.h>
-#include <soc/northbridge.h>
 #include <console/console.h>
 #include <arch/bert_storage.h>
 #include <cper.h>