GitLab

Change-Id: Iab2737940f07afb4f5a29ff50e6cb2a22027c51b
Signed-off-by: Bob Moragues <moragues@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30094Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

They were not originally printed, and serve no good purpose, so let's
remove them again.

Change-Id: I4e00477f2e143f93fd27ba6a083977a667a3eb48
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/28829Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

disable_all_smi_status() was not clearing SMI_EVENT_STATUS. This caused
us to complain in the eventlog (ELOG_SLEEP_PENDING_GPE0_WAKE) and then
wake early from sleep when waiting for a cr50 reset to turn on a cr50
update.

BUG=b:121203745
TEST=Careena remains in S5 until cr50 reset after cr50 update, and
ELOG_SLEEP_PENDING_GPE0_WAKE is no longer seen in eventlog.

Change-Id: I2eec014109249d5c3574c4dbdec5569e2a0bfc8e
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30304Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>

New emmc DLL values for Yorp.

BUG=b:120561055
BRANCH=octopus
TEST=Boot to OS, chromeos-install, mmc_test

Change-Id: I771c959a15959160224f056c0a16aa65bfbba94e
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/30073Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>

Sometimes the platform boots in an invalid state, that will cause
FSP-M to fail. As a board_reset() doesn't fix it, issue an full_reset()
as soon as the IA32_FEATURE_CONTROL MSR is locked at beging of romstage.

Tested on wedge100s. After full reset the system behaves as normal.

Change-Id: I1a382b8fb650311b0c24b48e0986d22edfa2d261
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30290Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>

When the old syntax is used, gerrit now respends with:

    remote: WARNING: deprecated topic syntax. Use %topic=TOPIC instead

Change-Id: I002bfc3e9c4b348379337bc386d3bdefb307679d
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/29983Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Change-Id: I9651b24dd68f9a5e324a4532c3cebac32aacca7e
Signed-off-by: Evgeny Zinoviev <me@ch1p.com>
Reviewed-on: https://review.coreboot.org/c/26885Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Describe state and assuptions made about x86_64 support.

Change-Id: I308a09b0eac269afd30df95ed3ea195238a6cfbe
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/30056Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

It's easy to misinterpret or miss altogether the instruction to
run 'make gitconfig', which will cause strange problems a few
commands later.  Revise the documentation to make it clearer.
Also adds a blurb further down with a link to find Gerrit
workflow docs.

detached from FETCH_HEAD
Signed-off-by: Michael Bacarella <michael.bacarella@gmail.com>
Change-Id: I49734c724c4d6da716a358cd849938ef14dab3b1
Reviewed-on: https://review.coreboot.org/c/30060Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Picture of mainboard wasn't displaying.
Signed-off-by: Michael Bacarella <michael.bacarella@gmail.com>
Change-Id: Ia70f5d5ad2fdf4c0e811ab92a817375a89694122
Reviewed-on: https://review.coreboot.org/c/30170Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Carl-Daniel made this script a long time ago but it never was picked up
in the tree. Now that USB debugging is way more common it makes
sense to include it.

I have made a number of changes to the original version:
* -h help text
* check for running as root
* enhanced readability (test -> if)
* new execution flow and refined output that better shows the device(s)
  attached to the debug port(s)
* handling of Intel rate-matching hubs
* hiding of (bogus) error messages from lspci and lsusb
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Change-Id: Iadf775e990f5c5f91a28d57e3331d1f59acee305
Reviewed-on: https://review.coreboot.org/c/9305Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Turn on power optimizer of PCH side DMI and SATA controller.

BUG=N/A
TEST=Build and boot up into sarien platoform, able to finish 100 cycles
of s0ix.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I41da2b4106d683945cdc296e2a77311176144f43
Reviewed-on: https://review.coreboot.org/c/30212Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

Expose the FSP interface to enable SATA and PCH side DMI power optimize
options. Actual step executed in FSP, step defined in cannonlake pch
BIOS spec(CDI# 570374).
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ic0c589bb21e56800090bc0c75a0256a0409efc78
Reviewed-on: https://review.coreboot.org/c/30211Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Add support for relocations on x86_64.
Required for 64bit romstage.

Change-Id: I1ff223d3476776297b501813a953356dd6fa9d67
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/30115Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>

Add support for 64bit rmodule, as required for relocatable
ramstage on x86_64.

Change-Id: I7fbb3b4c0f76ce82c090b5f16f67a728b6bf94a5
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/29874Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

SaGv(system Agent Dynamic Frequency) have 4 settings
Disabled, Fixedlow, Fixedhigh, Enabled.
This patch add all 4 settings in enum definition and
used in devicetree.

BUG=None
Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Change-Id: I8f3b56f4d2bea1836373cc505ef5147144100b95
Reviewed-on: https://review.coreboot.org/c/30305Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Change-Id: I01509c2fa2c127b77ae72b8b0aaac0f826b0bedd
Reviewed-on: https://review.coreboot.org/c/29859Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com>

Use 'BAR 1' for the bar1 structure fields.

BUG=N/A
TEST=Intel CherryHill CRB

Change-Id: I1d1278f549fc8a2f3e743e2e2019d3e5f7005614
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/30277Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>

Use 2T memory timings on Liara for all board IDs.

BUG=b:116082728
TEST=Build & boot on Liara

Change-Id: I5814e63db35cf7761f4f20792b0f3cf4120a1b60
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/30285Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@google.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>

Set CONFIG_NO_FADT_8042 to avoid probing for the 8042 controller.
This speeds up boot on nocturne by 1.3 seconds:

  Before change:
  [2.162266] EXT4-fs (mmcblk0p3): mounting ext2 file system using
  	the ext4 subsystem

  After change:
  [0.867735] EXT4-fs (mmcblk0p3): mounting ext2 file system using
  	the ext4 subsystem

BUG=b:120960844
BRANCH=none
TEST=build, flash, and boot nocturne; check dmesg to verify that
boot is faster and that you don't see the following log in dmesg:
	[0.671501] i8042: Probing ports directly.

Change-Id: I62a16e6de5e74fa17970d9967f6d1628497ec1d3
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/30283Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

The TXE PCI device serves no function under Linux, and doesn't
work properly under Windows, so disable/hide it from the OS.

Test: Boot Windows 10 on google/squawks, verify TXE not visible
under Device Manager.

Change-Id: Idaa152e15106b826fd5aa787090acd45719f4228
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30235Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Commit 73b723d7 [google/cyan: Switch Touchpad and Touchscreen...]
in additon to changing the touchpad/touchscreen interrupts from
edge to level triggered, also marked them as maskable. This not only
broke the touchpad functionality, but caused issues with the touchpad
as well.  Revert the touchpad to being non_maskable for all cyan
variants with a touchscreen.

Test: boot GalliumOS on google/cyan with a range of kernel versions
(4.15.18, 4.16.13, 4.17.x, 4.18.x) and verify touchscreen functional,
touchpad working properly (not jittery)

Change-Id: I0e0357912f9404af7d0f4e7938a1a94c74810b37
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30236Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

This board doesn't have a UART on the super I/O. Selecting this option
speeds up boot time from ~493 ms to ~416 ms.

Change-Id: I1d84f373831381da79022638e1082adf68f47aad
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30148Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

Quoting from the RISC-V Privileged Architecture manual version 1.10,
chapter 3.1.11:

    The FS and XS fields use the same status encoding as shown in Table
    3.3, with the four possible status values being Off, Initial, Clean,
    and Dirty.

    Status   FS Meaning    XS Meaning
        0    Off           All off
        1    Initial       None dirty of clean, some on
        2    Clean         None dirty, some clean
        3    Dirty         Some dirty

Change-Id: If0225044ed52215ce64ea979d120014e02d4ce37
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/28987Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

When I debug with HiFive Unleashed, I found that hart 4 could not be
running. Then find the duplicate MAX_CPUS definition. The correct
MAX_CPUS is located in src/soc/sifive/fu540/Kconfig

Change-Id: I583f6ba548daeeb6c7e341dc3fa8817e7dec5697
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/c/30179Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Change-Id: Ia7f409ebc7e50383a7e445ef8806953347501dab
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/30175Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>

Change-Id: Ide30a7396b6248e2037041e177dc8514533718a4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30240Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

The following was tested:
- Using two DDR2 DIMMs
- S3 sleep and resume (on SeaBIOS it needs sercon disabled)
- Ethernet NIC
- Libgfxinit (native res and textmode)
- SATA
- USB
- 800MHz FSB CPU (Pentium(R) E5200 @ 2.50GHz)
- PS2 Keyboard
- Serial output

TODO:
- Add ACPI code for SuperIO devices (done in a follow-up patch)
- Add documentation

TESTED with SeaBIOS (sercon disabled), Linux 4.19

Change-Id: I483e1143e4095b8a58fed142d31ca7f233a854e2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30239Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

There are no public datasheets for this SuperIO. The results are from probing
the registers manually.

Change-Id: Ie5659533c5f224603f918d17942a7057e6701222
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30238Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

Change-Id: I85b5aef758a1ed30c46ed0adabec3293edb0f3fd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30241Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>

Commit c37b0e3d [soc/intel/skylake: Generate ACPI DMAR table]
only generates DMAR tables for boards using FSP 2.0, which
leaves out Skylake Chromebooks, which use FSP 1.1.

Correct this omission by adding the same functionality for
FSP 1.1 boards.

Test: build/boot on U-series Skylake Chromebook, observe
IOMMU fully functional with intel_iommu=on kernel parameter.

Change-Id: I68837f58aac357fa3f58979fe92d8993fae58640
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30230Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

Update HDAenable bit in Fsp memory init UPD data base on devicetree
settings.

BUG=N/A
TEST=N/A

Change-Id: I5159c00a855a2a9516714ccee8ee9933465c5063
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30097Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

Define SATA mode to AHCI mode instead of 0, make devicetree more
readable.

BUG=N/A

Change-Id: I903545d9487c1409f9008407fe5bee6aa4959b98
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30095Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

FSP support two SATA modes as AHCI mode (0) and RAID mode (1), make it
more clear in header file.

Change-Id: I1edcadc0048df839da145260b60f9f7720d981fe
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30093Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

CPU ratio will be fixed to non-turbo max value if CpuRatio UPD had been
set to zero.

BUG=N/A
TEST=Boot up into sarien system, cat /proc/cpuinfo and cpu frequency is
changing.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I3e82293c8b6027ddf9a528d0654fe46f233dcb82
Reviewed-on: https://review.coreboot.org/c/30216Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

When I added the cmos.layout file, I did not realise that the
southbridge code cleverly emulated the "keep state" option.

Tested on an ASRock H81M-HDS. The `Keep` option works as it should.

Change-Id: I908e59d1e1eedefa6610e7f980afc3c04390a519
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30102Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

The deleted line crept in with commit 562db3bb ("libpayload: find
source of input characters").

Tested on an ASRock H81M-HDS with `power_on_after_fail` set to `Disable`
via CMOS. After this patch, the system no longer powers on as soon as
power is restored after a power failure.

Change-Id: Ie9d9dab9885b285db1c5094c2c8d62aae551f1e7
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30101Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

RAM is reserved for Chromeos even when Chrome is not used.
Use CONFIG_CHROMEOS to determine if RAM must be reserved.

BUG=N/A
TEST=Intel CherryHill CRB

Change-Id: I3f55bf96ab2ec66cddbb54de03455a9bfd194682
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29332Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Enable ELAN Touchpad and Disable ALPS Touchpad

BUG=b:119628524
BRANCH=master
TEST=ELAN Touchpad can work normally.

Change-Id: I7839459a70768fa95ba4871b1915d2ea86419bbb
Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30194Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>

Fix typo of "VGOIO" back to "VGPIO".
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ia2b7cb0e5fe2817acc3e3f4656b98dc2462b397f
Reviewed-on: https://review.coreboot.org/c/30147Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>