GitLab

Fix tables and minor markdown bugs.

Change-Id: I2ceb9614b516cbea19ab5e15ea7efabdfa3424bd
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/26276Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

These methods had unused arguments and could be corrected by
setting the correct number in the method initializer.

Change-Id: I86606cfa1c391e2221cee31994e83667fa9ead61
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26125Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Since the SIOW method doesn't use any arguments, don't pass it any,
and initialize it as not using any.

Change-Id: I3fa2ab8afb7d09c176a94bbd1db27587c36030cd
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26126Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>

This adds the following changes to the blobs repository:

78a02a7 cpu/intel: microcode: add license agreement
1d37962 cpu/intel: add microcode updates 20180312 for new CPU models
8b8bbce cpu/intel: apply microcode updates 20180312 to currently tracked models

In short: Bump Intel microcode updates. They include spectre/meltdown
mitigations.

Change-Id: I141f4446bc4e3bff5641bc39b70b299dc09ac8a7
Signed-off-by: Martin Kepplinger <martink@posteo.de>
Reviewed-on: https://review.coreboot.org/26270Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>

Make use of i8042 driver to add PS2 mouse driver support.

Tested on Lenovot T500.
The touchpad can be used to drive the mouse cursor.

Change-Id: I4be9c74467596b94d64dfa510824d8722108fe9c
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18597Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>

Program the Super I/O to turn the machine on or restore its power state
when AC power is restored.

Based on code from src/superio/nuvoton/nct5572d/superio.c.

Change-Id: I1f3432f43b0784c3696bf1d7233b83d3a203af20
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-on: https://review.coreboot.org/25463Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

This field is not provided by the soc code so add it.

TEST=Check the output of 'dmidecode -t memory'

Change-Id: I6fdf3520da62336a5c654575ed8d1f33eb4f4dc5
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/24912Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Make use of i8042 driver in keyboard.c.

Required to add PS/2 mouse support.

Tested on Lenovo T500.

Change-Id: If60b5ed922b8fc4b552d0bfd9fe20c0fd6c776bf
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18596Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Currently, adding a payload to CBFS using the build system, the warning
below is shown.

    W: Unknown type 'payload' ignored

Update payload type from "simple elf" to "simple_elf" and rename the
word "payload" to "simple_elf" in all Makefiles.

Fixes: 4f5bed52 (cbfs: Rename CBFS_TYPE_PAYLOAD to CBFS_TYPE_SELF)
Change-Id: Iccf6cc889b7ddd0c6ae04bda194fe5f9c00e495d
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26240Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Move keyboard.c into i8042 folder.

Change-Id: Idd30a9082e48a451d9fe5ead3f3dda4e6396b50c
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18595Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Add a common i8042 driver that uses multiple overflowing
fifos to seperate PS/2 port and PS/2 aux port.

Required to support PC keyboard and PC mouse at the same time.

Tested on Lenovo T500.

Change-Id: I4ca803bfa3ed45111776eef1f4dccd3fab02ea39
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18594Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

It’s unclear why this option was commented out. Activate the line, and
copy the CMOS layout and defaults from qemu-i440fx.

TEST=Boot 2.11.1(Debian 1:2.11+dfsg-1ubuntu7) and see that nvramcui
     works. A changed value doesn’t survive a reboot though.

Change-Id: Ieef86f092d323c68a6d2d0cc6c04c395f743a935
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/26265Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Fix dual LAN sku can't inherit correct MAC from VPD setting.

BUG=b:77836343
BRANCH=Fizz
TEST=Program the mac address to VPD in shell
     vpd -s ethernet_mac0=<mac address1>
     vpd -s ethernet_mac1=<mac address2> && reboot the system.
     Ensure the MAC address was fetched correctly by ifconfig command.

Change-Id: Ic357a3f1435d6d08107520e40872f1003ef2edf3
Signed-off-by: David Wu <david_wu@quantatw.com>
Reviewed-on: https://review.coreboot.org/25587Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

It is a special case for the Fizz firmware branch, when the device index
is 1, it will check "ethernet_mac" first and then "ethernet_mac0".

For single NIC: config.device_index = "1", maps to "ethernet_mac"
For multiple NICs: config.device_index = "1", maps to "ethernet_mac0"

BUG=b:77836343
BRANCH=Fizz
TEST=Add device index in device tree &&
     Program the mac address to VPD in shell
     vpd -s ethernet_mac=<mac address> or
     vpd -s ethernet-mac[0-9]=<mac address> && reboot the system.
     Ensure the MAC address was fetched correctly by ifconfig command.

Change-Id: I67fd2e999c8f9d8782f294fcafa84b8da970a3a6
Signed-off-by: David Wu <david_wu@quantatw.com>
Reviewed-on: https://review.coreboot.org/26051Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Change-Id: I67c4f579f898a709dde3fab6bab1474a721da770
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/18258Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Change-Id: Icc3973dfc7217ca649fb4151ccdea5461a550bb8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26272Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>

Registers IA32_MCi_xx are defined as architectural MSRs
since "P6 Family Processors" and should have model-agnostic
indexing.

Note that in IA32 architecture manual, names of these MSRs are
similarly swapped in the table of Intel Core Microarchitecture.
I take this is an error in the documentation only, and it got
copy-pasted across different CPU family files in the utility.

Change-Id: I227102875b5c3d6ac144ed23a3085f3c37dabd4a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26269Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Change-Id: I46cd986f4914b214156da49db37ecfa749386ce8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26268Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>

Not everything non-intel is AMD.

Change-Id: I06d6fbaa0b4f2c9e61d9b3b4aeeb349a91aa090e
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/18255Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Use of device_t has been abandoned in ramstage.

Change-Id: Ie366a49045940747eb5cc1e38316cce31c5774cb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26251Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

Use of device_t has been abandoned in ramstage.

Change-Id: Id3289c891e8a81c750fc3f5fad0fd16c0f2702fe
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26195Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

Braces {} are not necessary for single statement blocks.

Change-Id: I2a2d8672fe3f53450dcfa53dc127b89b4aa6b75e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26201Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

In some cases callers want to know if a file
exists and, if so, what its type is.

Modify cbfs_locate so that if the pointer is non-NULL,
but has the value 0, the type of the file that
matches the name will be returned.

Change-Id: Ic1349d358c3054207ccbccf3825db56784327ad0
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/26279Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Change-Id: Ib215aa17dd20112946b74a1b63ce8a735388873c
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/24927Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Update the gpio configuration structure to the intelblock format.
The resulting configuration is functionally similar (even if some
bits are not identical).

Change-Id: Ide515424c6e1b0cb560b52a7f12909f23fd41e06
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/25424Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

The intelblock code is common code already used by appololake and
cannonlake platform. The denverton platform also use a similar gpio
controller so the intelblock code can be used as well.

Change-Id: I7ecfb5a3527e9c893930149f7b847a41c5dd9374
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/24928Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

In order to use the shared code in intelblock, this patch renames the
denverton specific implementation to not use the same names (for files
and types).

- rename pad_config to remove conflict with soc/.../intelblocks/gpio.h
- rename gpio.c, soc/gpio.h to not conflict with intelblock

Note: There is no functional change in this patch.

Change-Id: Id3f4e2dc0a118e8c864a96a435fa22e32bbe684f
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/24926Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Add a static CSS file to remove annoying scrollbars on rst code tables.

Change-Id: I436b36fb7ee9856c7d6ad8534cd0610b7f071b17
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/26263Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>

All those symbols are part of /include/symbols.h file hence
removing from /security/vboot/symbols.h

Change-Id: Id968186e28d6b772a1a6bca200a852407324d6e3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26274Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

* Introduce pci_devfn_t on all arch
* Add PCI function prototypes in arch/pci_ops.h
* Remove unused pci_config_default()

Change-Id: I71d6f82367e907732944ac5dfaabfa77181c5f20
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25723Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

The NPCD378 can be found on at least:
* HP Compaq 8200
* HP Compaq 8300

The datasheet is not publicly available, as HP implements lots of
custom hardware. Add basic support for it, based on HP Compaq 8200.
The first eight LDNs seem to be standard nuvoton compatible, except for
LDN4, which is used to control front LED and power in ACPI S3.

LDN8 provides access to HP's proprietary HWM which is accessiable at the LDN's
IOBASE with a size of 0x100 bytes.
The HWM consists of 16 pages with each holding 0xff bytes. The pages can be
selected by writing the page index to IOBASE + 0xff.

TODO:
Reverse engineer the HWM to support fan control.

WARNING:
The remaining LDNs have been guessed and might be wrong!

The serial has been tested and is working.

Change-Id: Ib497fd41b88e9c159eeeffa69bc2bfdccee9cb38
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/25384Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

This patch ensures that user can pass a function with given argument
list to execute over APs.

BUG=b:74436746
BRANCH=none
TEST=Able to run functions over APs with argument.

Change-Id: I668b36752f6b21cb99cd1416c385d53e96117213
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25725Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

In order to extend the MP callback infrastructure prepare for
easier changes by making the AP callback get signalled by a
single pointer to a local variable on the signaller's stack.
When the APs see the callback they will copy the structure
to a local variable and then set the acknowledgement by
clearing out the slot.

The reading and writing to the slots were implemented using inline
assembly which forces a memory access and a compiler barrier.

BUG=b:74436746

Change-Id: Ia46133a49c03ce3ce0e73ae3d30547316c7ec43c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/26043Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Change-Id: Ie32a008ce636b8eee6ed90c364978f7d37f4bfb2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19876Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Change-Id: Ifef905f5115ffc826b1a355e54c4b1ca818e56fa
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19875Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Adapt the programming of initial DLL values for DDR3.

Change-Id: I67e48b4ae6f2076399133ba7b98ab1dfc0e0ab08
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22993Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

Also throws in some minor fixes like the wrong conditional for
bankmod and using real CAS when programming MCHBAR(0x248).

Change-Id: Ia2494684ec66d84d4dc27c6a6b425a33ace6e827
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19873Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

Adds nmode to the sysinfo struct as it is needed later on.

Change-Id: Ia2ca4a200a1c813b2133eb1004fbe248fa3de9ce
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19872Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

A few values were wrong, but it does not seem to matter all that
much.

Change-Id: I86b70e06c81817854994b7feddf9f3638fd16198
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19871Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

This memory controller supports both DDR2 and DDR3 memory, yet many
functions have ddr2 in their name while not being ddr2 specific.
This patch renames those to avoid confusion.

Change-Id: Ib3d10014f530905155e56fc52706edb4ab9f5630
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19870Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>