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Change-Id: I990969cf1389c19032c4a0fafbdef45b9d6d1e8b
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/22257Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Change-Id: Id01b72a2194ebf3359a11c3ff382efaedf28f9e1
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/22255Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

They both have a device id of 0x3c. The former is part of the PCI chip set
accessible via port 0x3f0 while the latter is a standalone LPC chip accessible
via 0x2e/0x4e depending on strapping.

They're not register compatible: the VT82C686 only provides a FDC, LPT and part
of UARTs.

The VT82C686 documentation suggests it has revision 0x00 while the VT1211
datasheet indicates 0x01. Nevertheless, the VT1211 I happen to have hs a
revision of 0x02. Thus the revision is probably not good enough to tell one
from the another.

Change-Id: Ic7529c84724c8d6b9eb75b863f1bceef5e4b52b5
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/22254Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Change-Id: I2c24c347c3e044397944ca2abbceb36f83483daf
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/22253Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

The `secimage` utility uses OpenSSL to calculate HMAC, which it does in
a rather unorthodox way, using deprecated `HMAC_CTX_init` API and
repeated calling of `HMAC_Init_ex` without a clear reason. The former
causes build errors with OpenSSL 1.1 while the rest of the
`HmacSha256Hash` function is confusing and overly complex.

Make `HmacSha256Hash` use a single OpenSSL API call. Test passed:
resulting signed binary remains identical.

Change-Id: Ib23c0ad96f9d8cc30ad357de8c0b0ba967c7d724
Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/23069Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Change-Id: Ic02c3a6265f11c1571369bc04371d28b6f989736
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21464Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

This source file was mostly copied from ga-945gcm-s2l but had
different IO decode ranges.

Change-Id: I54cb165000fad6984edf13fb33519fb9c9f0350f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23134Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

Things cleaned up in this patch:
* Add macros for the GENx_DEC registers;
* replace many magic numbers by macros;
* remove many writes to DxxIP since they were 'setting' reset default
  values;
* fix some comments about decode ranges.

Change-Id: I9d6a0ff3d391947f611a2f3c65684f4ee57bc263
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21065Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

Use the variable `device` instead of `dev` in the predicate of
the if condition, as `dev` is not changed in the for loop.

The for loop was added in the following commit.

    commit 8fed77ae
    Author: Scott Duplichan <scott@notabs.org>
    Date:   Sat Jun 18 10:46:45 2011 -0500

        ASRock E350M1: Configure SB800 GPP ports to support onboard pcie nic

        Reviewed-on: http://review.coreboot.org/44

The assumption that the devices are ordered in the tree seem to
hold in this case (although it is not ensured) and therefore at
least with the ASRock E350M1 no (visible) change is experienced as
the children are all of type `DEVICE_PATH_PCI`.

Change-Id: Iaa2fa13305dbe924965d27680cd02fe30c2f58a5
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/2562Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Add code to support the board ASUS AM1I-A. Tested with multiple payloads
and OSes with satisfactory results. S3 suspend/resume works fine with
Linux but has issues with Windows (an exception is thrown). However,
after manually rebooting, Windows resumes the suspended session.

* Tested with: SeaBIOS 1.11 + Linux 4.10 - OK
* Tested with: tianocore vEDK2017 + MS Windows 8.1 - OK
* Tested with: FILO 0.6.0 - hangs after showing the banner

Details are going to be published on the board's status page.

Change-Id: I3d9432849560df81536bbb2ce4c87cd265b820f7
Signed-off-by: Gergely Kiss <mail.gery@gmail.com>
Reviewed-on: https://review.coreboot.org/23002Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

Due to the lack of a datasheet, defaults are shown as
"not available (NA)" in the register dump.

Change-Id: I6baaf5dd95453fb1265425f357ea16c710c006ba
Signed-off-by: Gergely Kiss <mail.gery@gmail.com>
Reviewed-on: https://review.coreboot.org/23084Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

GPIO 90 is being used as a GPIO.  The IOMUX register is set correctly,
but these additional registers need to be set to use it as a GPIO.
- Split structures into variant specific versions.  These will be
moved into the variant tree in a follow-on patch
- Set GENINT_DISABLE bit
- Disable interrupts for this GPIO.

BUG=b:71867096
TEST=Build and boot grunt.  Verify registers are set correctly.

Change-Id: I4b8d12720167b298ee6e0acf80edf414539975b0
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23228Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

BUG=b:71867096
TEST=None

Change-Id: Ic8111d34355e6667c37a51d285ebb50c1659f4e5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23227Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

The GPIOs that are being set low had the wrong value getting set.
FCH_GPIO_OUTPUT_VALUE was being set instead of FCH_GPIO_OUTPUT_ENABLE.

BUG=b:70234300
TEST=Build and boot Grunt

Change-Id: I16792b76252506a43aac92738b04096ae3fde01c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23224Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>

Grunt and Kahlee touchpads are on different i2c busses; I2CC and I2CD,
respectively.

Since grunt is the 'baseboard', put its configuration under baseboard, and
include it from the grunt variant.

BUG=b:71820409
TEST=Boot grunt to kernel, use evtest to test trackpad.
TEST=Boot kahlee to kernel, use evtest to test trackpad.

Change-Id: I1aeacf9a840342e73c1e219a825b39a124b4dd57
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/23232Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Grunt and Kahlee have different audio codecs.

Create a new audio .asl for the baseboard for grunt's codec, link
to it from the grunt mainboard, and move the kahlee codec table
from the baseboard mainboard to its own .asl in variant/kahlee.

Note, we can't use the generic drivers due to the PCI scope
expectation. The AMD I2C are not PCI devices.

BUG=b:69397774
TEST=Codec driver loads. Check dmesg.

Change-Id: I1cc245357d1f3d444e5a5012466eaa5d75d637eb
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/23226Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Move the apci/ to the baseboard and move mainboard.asl to
each variant.

BUG=b:71873651
TEST=build
BRANCH=none

Change-Id: I8a829f2946e4b280cd78574eb8dbda6c2a9a1028
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23229Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>

The ACPI unique identifier (_UID) should be unique.

This doesn't actually matter much for Linux, though, since the kernel
can handle it when the BIOS doesn't get this right.

See:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=b4b6cae2f36d92b31788f10816709d5290a1119a
 b4b6cae2f36d ACPI / platform: use ACPI device name instead of _HID._UID

Change-Id: I8b1b3143174584a93f3d45bf482b8922b3f0ec12
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/23233Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>

This reverts commit 0f5651584ebb8e2ccfa151275bfd2f70e74bae9b.

This is not the correct fix for the heap allocator.
It looks like the root cause is in the buffer size of the
deallocate function.

Change-Id: I33c479a30d89a665677d3e4914194ae8136504af
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23245Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chris Ching <chingcodes@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>

Meowth uses GPD_2 as a dedicated lan_wake pin, so GPD_2 must
be set to use NF1 instead of gpio.

BUG=b:64395641
BRANCH=none
TEST=none

Change-Id: Iadf7158a792dfae0ea5e824d197a558524cdb5fd
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/23222Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Intense PC uses FCBGA1023 socket, not rPGA989. Correct the socket
in the devicetree.

Change-Id: Ie657af2f51dfb7add90b19b26c0c37d312d59821
Signed-off-by: Hal Martin <hal.martin@gmail.com>
Reviewed-on: https://review.coreboot.org/22762Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

Enable the UART via SMSC SIO1007 SuperIO, this allows you to see boot
boot messages from coreboot over the integrated RS-232 port (requires
use of included dongle).

Change-Id: I11a4c532ed73a0cf27d6e7bef6e04035c3942567
Signed-off-by: Hal Martin <hal.martin@gmail.com>
Reviewed-on: https://review.coreboot.org/22737Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

The code is based on autoport and that for 8470p.

Tested:
- CPU i5-3437U
- Slotted DIMM 8GiB
- Soldered RAM 4GiB from Hynix (There may be more models here)
- Onboard USB2 interfaces (digitizer, wlan slot, wwan slot, camera)
- Mini pci-e on wlan slot
- On board SDHCI connected to pci-e
- USB3 ports
- USB3 hub on dock (connected to USB3 port 1)
- NVRAM options for North and South bridges
- S3
- TPM1 on LPC
- Linux 4.13.13-1 within Debian GNU/Linux testing, loaded from
  SeaBIOS, or Linux payload (Heads)

Not work:
- An "NFC" device connected to LPC

Not implemented yet:
- Detecting the model of Soldered RAM at runtime, and loading
  the corresponding SPD datum (3 observed) from CBFS

Change-Id: Iba9c361591697e6a2b3b7b485f7f1649c2a83524
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/22972Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

Change PAD_CFG_GPI_GPIO_DRIVE to PAD_CFG_GPI_APIC for GPIO D9 to
meet the requirement of DA7219 IRQ pin.

BUG=b:70646770
BRANCH=none
TEST=Use aplay and arecord to verify headphone function.

Change-Id: Id6cff8325c4c7f02f6f4df547fde286e2ef83d5c
Signed-off-by: Kaiyen Chang <kaiyen.chang@intel.com>
Reviewed-on: https://review.coreboot.org/23160Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

We check for NULL from the return of function acpi_device_path
before passing it to acpigen_write_scope to avoid NULL pointer
dereference.

Change-Id: I997461c9b639acc3c323263d304333d3a894267c
Found-by: Klockworks
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/23094Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

According to Intel document #559100 KBL EDS v2.8, section 7.2
DC specifications, the IccMax setting for KBL-U, KBL-U42 and
Celeron/Pentium are different. This patch overrides the IccMax
settings for KBL-U/R/Y since device tree could not handle all
KBL-U/R combinations when multiple SKUs are adopted in a project.
Besides, it is inefficient to maintain the same code for all
variants. Hence, place it in the common code so that all variants
could leverage the benefits.

+----------------+-------------+---------------+------+-----+
| Domain/Setting |  SA         |  IA           | GTUS | GTS |
+----------------+-------------+---------------+------+-----+
| IccMax(KBL-U/R)| 6A(U42)     | 64A(U42)      | 31A  | 31A |
|                | 4.5A(Others)| 29A(Celeron)  |      |     |
|                |             | 32A(i3/i5)    |      |     |
+----------------+-------------+---------------+------+-----+
| IccMax(KBL-Y)  | 4.1A        | 24A           | 24A  | 24A |
+----------------+-------------+---------------+------+-----+

BUG=b:71369428
BRANCH=None
TEST=Remove icc_max setting from devicetree & emerge-fizz coreboot
     chromeos-bootimage & Ensure the KBL-U42, KBL-U22 and Celeron
     SKUs are identified correctly and IccMax settings are passed
     to FSPS correctly.

Change-Id: I291462b73d3fbd17f17975de7fd77dc48ca99251
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/23060Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

The EC does enable bluetooth on wifi cards and BDC at the same time.
Check the new Kconfig to support bluetooth on wifi in case no BDC
is installed and the BDC detection fails.

Change-Id: I23f14c937252a296dc543db49ec9e093e7e24604
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21578Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

TCPU:
  _CRT: 100
  _PSV: 93
  _TRT: 100/5(s)
TSR0:
  _CRT: 83
  _PSV: 70
  _TRT: 100/10(s)
TSR1:
  _CRT: 73
  _PSV: 67
  _TRT: 100/30(s)

TCC: 6 for 94'C

PL1:
  max: 15W
  min: 3W

BUG=b:70294260
BRANCH=master
TEST=build
Change-Id: Ie17f4395d2199009fd68a600d818f2be54bc8935
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/23155Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

Fizz has external Lan on PCIE port.
The Lan device on PCH is not used.

BUG=b:70889517
Change-Id: I99894bedec14a44724ac7c22d0c894132a795b78
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/23180Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

This patch adds the EC_GOOGLE_CHROMEEC_SWITCHES option so that we
use the common switch.c file

Change-Id: I93a2ba63015db17989c89ce1b5897de6a93e201f
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/23131Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

This patch adds recovery cache.

TEST:glkrvp boots with this change and also FAFT test
     firmware_CorruptRecoveryCache passes.

Change-Id: I9b32628d814693fb0591fc3750348d48cf9e26f1
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-on: https://review.coreboot.org/23067Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

Digitizer power is not controlled by SoC. Also, since the digitizer
uses I2C-HID driver in Linux kernel, the device is put into sleep
anytime system is suspended. Thus, there is no need to control the
reset gpio using ACPI power resource.

TEST=Verified that digitizer device is properly detected on boot-up
and after suspend/resume.

Change-Id: Id11b8412d0ac48b2701d53b0a22ad3b747b544ec
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/23212Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Instead of duplicating code in each mainboard that supports HDA use
the common driver and provide the HDA verb table.

This was compile tested for both variants with "abuild -t intel/kblrvp"

Change-Id: Ie3bab7aabcfa040935062b7764853df8fb19b04d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/23188Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

There is common HDA code in soc/intel/common that provides generic
HDA support functions, but it does not provide a driver.

This change adds a common block driver for HDA that provides a
ramstage driver for SOCs that need to initialize an HDA codec.

This was tested on a board with an HDA codec to ensure that it
properly detected it and ran the codec init steps.

Change-Id: I41b4c54d3c81e1f09810cfaf934ffacafca1cf38
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/23187Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

A side effect of using the common MTRR assignment code is the flash
device loses its WP setting and is no longer cacheable.  After MTRR
setup, reenable the setting for the duration of POST.

TEST=Run on Kahlee and inspect MTRRs prior to AmdInitLate()
BUG=b:70536683

Change-Id: Ib4924e96e2876e1e92121bb52d1931ead723d730
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23205Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>

- Add pen device property into devicetree.cb.
- Set GPP_C9 to 0 as default.

BUG=none
BRANCH=master
TEST=emerge-nautilus coreboot and check pen device operation
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Change-Id: I050671c8b46fd92b1dd9164be2646727cd67da9f
Reviewed-on: https://review.coreboot.org/23010Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

The heap allocator would try to split a buffer node that
was too small for another node. In the failing case, the buffer
node was 0x140 bytes and the requested size was 0x133 bytes.
The logic would check that there was room for the header and
buffer and try to split the buffer node. The buffer node header
is 0xC bytes, so 0x13F bytes are need. The problem is that it didn't
leave room for another node header and a little space for a buffer.

BUG=b:71764350
TEST= Boot grunt.
BRANCH=none

Change-Id: Iece5e12d5787415a335bb953985331a5dc312152
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23211Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>

The Port initializer had been changed from PortDisabled to PortEnabled,
but engine inializer hadn't been updated from PcieUnusedEngine to
PciePortEngine.  Update this so the port works.

Also change disabled port to PcieUnusedEngine.

BUG=b:71818026
TEST=PCIe device now shows up on D2F4

Change-Id: I11eb8c1fbad12fa9cf34d758a4ef3c22ef8ba4f7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23210Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Chris Ching <chingcodes@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

After running `lint-stable` in the pre-commit hook, its result is
ignored. This behavior was introduced in commit b18f522b
(lint/gitconfig: Enable checkpatch.pl checking of commits) and it
doesn't seem intentional. This issue was also mentioned in the revert
discussion (https://review.coreboot.org/c/coreboot/+/17440).

Enable `errexit` mode of the shell so that the hook fails when an error
occurs in any of the tests. Also, enable `nounset` mode to catch typos
easier.

Change-Id: I749963167660ea6a1a04d40a14ad1113e82f0f86
Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/23130Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

If using type-C charger, then PsysPl2 may be lower than barrel jack
value of 90W, so need to override value to the max power of type-C
charger.

BUG=b:71594855
BRANCH=None
TEST=Make sure that PsysPL2 value set to 60W with zinger, but 90W
     when using proper barrel jack adapter on and i7.

Change-Id: If955b9af0e23f47719f001f1d73ec37113937cea
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/23182Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>