GitLab

It never made sense to have bootblock_* in init, but
pirq_routing.c in boot, and some ld scripts on the main
level while others live in subdirectories.

This patch flattens the directory hierarchy and makes
x86 more similar to the other architectures.

Change-Id: I4056038fe7813e4d3d3042c441e7ab6076a36384
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10901
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

Change-Id: I26f1bbf027435be593f11bce4780111dcaf7cb86
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/10586
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

If .git doesn't exist, try to fetch the coreboot version from a file, before
falling back to a hard-code.

Change-Id: Idee8019c9a2b766fe69535367614c5254498335a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10908Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)

Change-Id: If2ba9ca48c809fe4f7dc0595a3cb3df168d630fd
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/10893
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Change-Id: I3218bfaaa64bcad54fe97c6f887025356ccc9356
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/10892
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Needed for the main() prototype

Change-Id: I921a77d8b131b751291d3a279b23ee18b13eca8d
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10862
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Change-Id: I1a8ce0b8ec291a5ddd8fdefcda24842e2a3c692d
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10861
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

This patch aligns the output of coreinfo with the output
of libpayload, and switches from using $(Q) to .SILENT

Change-Id: I6c3cdda7febc02bab9195fc98f46490c0d478a9a
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10744Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)

LDO2 regulator is used as an always-on reference for the droop alert
circuit. Set output voltage to match kernel settings.

CQ-DEPEND=CL:284649
BUG=chrome-os-partner:42305
BRANCH=None
TEST=Compiles successfully and boots to kernel prompt

Change-Id: I5ef4e266d8ec278dadffa846af8dc49b6d18c37e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 611465f6248cba0ddce0083b431cb7ee17bc4b4c
Original-Change-Id: I58cc473452b871392d813387707a0b8288e46561
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/284879Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10900Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)

Define custom stage_entry to apply workaround for A57 hardware issue
for power on reset. It is observed that BTB contains stale data after
power on reset. This could lead to unexpected branching and crashes at
random intervals during the boot flow. Thus, invalidate the BTB
immediately after power on reset.

BUG=chrome-os-partner:41877
BRANCH=None
TEST=Compiles successfully and reboot test does not crash in firmware
for 10K iterations.

Change-Id: Ifbc9667bc5556112374f35733192b67b64a345d2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bc7c2fec3c6b29e291235669ba9f22ff611064a7
Original-Change-Id: I1f5714074afdfee64b88cea8a394936ca848634b
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/284869Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10899
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

This allows SoCs/CPUs to have custom stage_entry in order to apply any
fixups that need to run before standard cpu reset procedure.

BUG=chrome-os-partner:41877
BRANCH=None
TEST=Compiles successfully

Change-Id: Iaae7636349140664b19e81b0082017b63b13f45b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 498d04b0e9a3394943f03cad603c30ae8b3805d4
Original-Change-Id: I9a005502d4cfcb76017dcae3a655efc0c8814a93
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/284867
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10897
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

BUG=chrome-os-partner:41877
BRANCH=None
TEST=Compiles successfully

Change-Id: I8a94176a3faacb25ae5e9eaeaac4011ddf5af6a1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 802cba6f28a4e683256e8ce9fb6395acecdc9397
Original-Change-Id: I3a5983d4a40466bc0aa8ab3bd8430ab6cdd093cc
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/284868Original-Reviewed-by: Yen Lin <yelin@nvidia.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10898
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Well, this is just embarrassing...

BRANCH=None
BUG=None
TEST=None

Change-Id: I7c443d2100b6861d736320ac14c1bd9965937a66
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 455e3784882ea1b76bcf8e17724869e37d9c629d
Original-Change-Id: Ia33e98aeaa8e78e3e3d2c7547e673a623ea86ce2
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/284596Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/10879
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Martin Roth <gaumless@gmail.com>

1. Make TTB_SIZE Kconfig option
2. Add Kconfig option for maximum secure component size
3. Add check in Makefile to ensure that Trustzone area is big enough
to hold TTB and secure components
4. Calculate TZDRAM_BASE depending upon TTB_SIZE and TZ_CARVEOUT_SIZE

BUG=chrome-os-partner:42319
BRANCH=None

Change-Id: I9ceb46ceedc931826657e5a0f6fc2b1886526bf8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a425d4978a467b157ea5d71e600242ebf427b5bb
Original-Change-Id: I152a38830773d85aafab49c92cef945b7c4eb62c
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/284074Original-Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10878
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

- extra rule for config.h creation
- include kconfig.h from libpayload
- libpayload symbols are conflicting with gcc builtins (e.g. log2)
- ALIGN() is already defined in libpayload these days
- move libpayload build directory under build/

Change-Id: I2aefdde26853253d58f6cf6e186e784871c1cb5b
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10717
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Print the old timB value to observes changes made.

Change-Id: Iecec4918f1d95560b6e7933a169ccce83fcf073d
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: http://review.coreboot.org/10891
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>

Issue observed:
Any memory DIMM placed in channel0 slots stops at "c320c discovery failed".
The same memory DIMM works when placed in channel1 slots.

Test system:
 * Intel Pentium CPU G2130
 * Gigabyte GA-B75M-D3H
 * DIMMs:
  * elixir 1GB 1Rx8 PC3-10600U M2Y1G64CB88A5N
  * crucial 2GB 256Mx64 CT2566aBA160BJ
  * corsair 8GB CMZ16GX3M2A1866C9

Problem description:
In case of good timmings (all bits are set) an offset of 3*64 was applied.
The following test (c320c discovery) failed only on those byte-lanes.

Problem solution:
Don't modify timB in case of good timings measured.

Final testing result:
The system boots with every DIMM placed in channel 0 slots.

Change-Id: Iea426ea4470640ce254f16e958a395644ff1a55c
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: http://review.coreboot.org/10889
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>

Remove whitespace errors.

Change-Id: If69244a5d47424e3e984fdf782ea9d2d3c466d86
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: http://review.coreboot.org/10888
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>

Add VGA pci device id 0x0152 for Intel IvyBridge CPUs.

Test system:
* Intel Pentium CPU G2130
* Gigabyte GA-B75M-D3H

Change-Id: Ia546fdf0cc3bbd4c0ef6b5fd969232f105bceb22
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: http://review.coreboot.org/10798
Tested-by: build bot (Jenkins)
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>

For hex and int type kconfig symbols, IS_ENABLED() doesn't work. Instead
check to make sure they're defined and not zero.  In some cases, zero
might be a valid value, but it didn't look like zero was valid in these
cases.

Change-Id: Ib51fb31b3babffbf25ed3ae4ed11a2dc9a4be709
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10886
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Platforms selecting the HUDSON_DISABLE_IMC symbol were showing the
warning:

warning: (BOARD_SPECIFIC_OPTIONS && BOARD_SPECIFIC_OPTIONS &&
CPU_AMD_AGESA_BINARY_PI) selects HUDSON_DISABLE_IMC which has unmet
direct dependencies (SOUTHBRIDGE_AMD_PI_AVALON ||
SOUTHBRIDGE_AMD_PI_BOLTON || SOUTHBRIDGE_AMD_PI_KERN)

By moving the definition of the symbol outside of the if block
and removing the default n, we can get rid of the warning without
changing the value for any platform.

Change-Id: I5c1bdfbcf3c5c44ee05b8c5e679f6854d784d8dc
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10680
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>

This protection didn't make sense to me - it seems like things would
probably break if printf wasn't defined anyway.

Change-Id: Ifb6bad46e193b35c13b7ad4946511fec74beff92
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10887
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

The script `util/crossgcc/buildgcc` was rewritten in commit 85b07d68
(buildgcc: move to a package centric user interface) and the switches
changed.  This patch does the following:

- IASL was split out of the gcc builds, so needs a target of its own.
- Add clang build target
- Update the build-ARCH targets as buildgcc -G no longer builds gcc.
- Rework all the targets to use common targets to call buildgcc
- Split the tempfile clean from the regular clean
- Change the 'all' target to leave the tempfiles until all architectures
are built so that if one fails and needs a rebuild, it doesn't have to
start from scratch.
- Add an all_without_gdb target
- Add clang build to all

Change-Id: I4ff720eab6d9b72d00757fd2b632e6d9a6c25aa3
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10679
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Kconfigs symbols of type bool are always defined, and can be tested with
the IS_ENABLED() macro.

symbol type except string.

Change-Id: Ic4ba79f519ee2a53d39c10859bbfa9c32015b19d
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10885
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Display a warning if CONFIG_HUDSON_FWM_POSITION is not inside CBFS.

This can be extended to other Kconfig values for CBFS.

Change-Id: I2423f7b361dda8aac5dab409fa7b656de486f635
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10683
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

This patch calculates the address where the chipset firmware descriptor
should be located and compares it against the actual value from Kconfig.
If the two don't match, it puts up a warning.

This could probably replace the config variable completely, but I wanted
to see how other people felt before doing that.  I seem to recall that
the value used to be calculated, so I figure that there must be a reason
it's done this way at this point.

If we do want to keep the Kconfig setting, this patch could also be
modified to just verify that the HUDSON_FWM_POSITION is inside the ROM
space.

Change-Id: I94addf463e2c694a94eef218ec855103a3bb5da5
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10682
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

The CBFS_BASE_ADDRESS can be compared against values used with cbfstool
to generate warnings.  This can help cut down on mistakes and debug
time.

Change-Id: I149007dd637661f799a0f2cdb079d11df726ca86
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10681
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Add macros to standardize math done in the Makefiles in a posix
compliant manner.

int-multiply takes an arbitrary list of values to multiply, the same as
the int-addition macro.

The other macros only work on two values at a time.

Change-Id: I3b754b9bcde26f33edc4f945d5af3d5444f383c7
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10874
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

rmodule.c: In function ‘rmodule_create’:
rmodule.c:287:29: error: ‘phdr’ may be used uninitialized in this function [-Werror=maybe-uninitialized]
        (phdr->p_vaddr + phdr->p_memsz))) {
                             ^
rmodule.c:204:14: note: ‘phdr’ was declared here
  Elf64_Phdr *phdr;
              ^

Change-Id: I94a235253610348484eef218ec855103a3bb5da5
Signed-off-by: Anatol Pomozov <anatol.pomozov@gmail.com>
Reviewed-on: http://review.coreboot.org/10881
Tested-by: build bot (Jenkins)
Reviewed-by: Francis Rowe <info@gluglug.org.uk>

While running ramstage with the EARLY_CBMEM_INIT config the timestamp
cache was re-initialized and subsequently used. The result was that
the ramstage timestamps would be dropped from cbmem.  The reason
is that the ramstage timestamps perpetually lived in ramstage BSS
never getting sync'd back into cbmem. The fix is to honor the
cache state in ramstage in the timestamp_init() path.

Also, make cache_state a fixed bit width to allow for different
architectures across the pre-ramstage stages.

TEST=Used qemu-armv7 as a test harness with debugging info.

Change-Id: Ibb276e513278e81cb741b1e1f6dbd1e8051cc907
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10880
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Fix up commit f44ac13d (Add TCPA table.) by adding an entry for
`CBMEM_ID_TCPA_LOG` to the macro `CBMEM_ID_TO_NAME_TABLE`.

Currently, printing the CBMEM table of contents the name is missing.

	$ sudo cbmem -l
	CBMEM table of contents:
	    ID           START      LENGTH
	[…]
	 6. 54435041   c7fa8ff8   00010000
	[…]

Adding an entry and rebuilding the utility cbmem, the name `TCPA_LOG` is
shown.

	$ sudo cbmem -l
	CBMEM table of contents:
	    ID           START      LENGTH
	[…]
	 6. TCPA LOG     c7fa8ff8   00010000
	[…]

Change-Id: I089ea714349e07b322330bc11f723cc031c61c56
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/10856
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Fix up commit f44ac13d (Add TCPA table.) by moving the entry to the
correct position so that all entries are sorted.

Change-Id: Ib68deb525a942051e1063ea2ec0a3e3b4a937024
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/10855
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Include the microcode files from the microcode subdirectory.

BRANCH=none
BUG=None
TEST=Build and run on cyan.

Change-Id: I4c8bf64d221d9ead18f1b7d6e1f01f61d88c9b25
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10873Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)

Update Makefile.inc to use the simplified CBFS image type.

BRANCH=none
BUG=None
TEST=Build and run on cyan

Change-Id: Ibb8413ab90b147e9d26d32639a8822c57ca54a46
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10871Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)

Useful information, record it in the destination directory,
together with .config.

Change-Id: Icf3282f61f502b37f9f06d7d5a0a630f49c96ed2
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10864
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Instead of having a second copy that already within 2-3 days
becamer quite outdated, use the same xcompile copy for coreboot
and libpayload, as we do with Kconfig already.

This requires a simple change to the top level xcompile to understand
both CONFIG_COMPILER_GCC and CONFIG_LP_COMPILER_GCC (only one of
them will occur at the same time)

libpayload's .xcompile target was moved later so that it can make use
of $(top)

Change-Id: I44001067f551cd0776dd303cbaeaa40eb3d5c1db
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10863
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Change-Id: Ida01506406d1d74211f0155a84c2b25dbaac5f1c
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10860
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Change-Id: I54650671adaef3bc129c662d6e972474c869afaa
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10859Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)

The include breaks compilation on ARM with clang.

Change-Id: I1ce0d58dbcbb8785c23739670c8c9574c329a81c
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10858Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)

This fixes issues with our clang reference toolchain on ARM.

Change-Id: Ib754941059285f15332bc694814aff6285969545
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10857Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)