- 18 Jul, 2018 3 commits
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Nick Clifton authored
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Nick Clifton authored
Fix typo in src-release.sh script. Update French translation for gold and Spanish translation for ld. gold * po/fr.po: Updated French translation. ld * po/es.po: Updated Spanish translation. . * (DEVO_SUPPORT): Fix typo in previous delta. (do_proto_toplev): Add --quiet option to configure command line.
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GDB Administrator authored
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- 17 Jul, 2018 1 commit
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GDB Administrator authored
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- 16 Jul, 2018 3 commits
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Nick Clifton authored
gold PR gold/23409 * symtab.cc (Symbol_table::define_special_symbol): Add check for version name on existing symbol. * testsuite/Makefile.am (ver_test_pr23409): New test case. * testsuite/Makefile.in: Regenerate. * testsuite/ver_test_pr23409.sh: New test script. * testsuite/ver_test_pr23409_1.script: New version script. * testsuite/ver_test_pr23409_2.script: New version script.
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Nick Clifton authored
* src-release.sh (DEVO_SUPPORT): Add test-driver and ar-lib.
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GDB Administrator authored
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- 15 Jul, 2018 1 commit
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GDB Administrator authored
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- 14 Jul, 2018 3 commits
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Nick Clifton authored
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Nick Clifton authored
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GDB Administrator authored
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- 13 Jul, 2018 2 commits
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Nick Clifton authored
* config/tc-arm.c (do_neon_mov): When converting an integer immediate into a floating point value, check that the conversion is valid. Also warn if the immediate is valid as both a floating point value and a bit pattern. * testsuite/gas/arm/vfp-mov-enc.s: Add instructions that use floating point bit patterns. * testsuite/gas/arm/vfp-mov-enc.d: Add regexps for the disassembly of the new insns.
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GDB Administrator authored
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- 12 Jul, 2018 6 commits
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Alan Modra authored
This is a followup to git commit 97196564 "Strip global symbol defined in discarded section". If a symbol defined in a discarded section was dynamic, that patch left .dynsym with holes (ie. all zero entries). For example, the following from libstdc++.so: Symbol table '.dynsym' contains 6090 entries: Num: Value Size Type Bind Vis Ndx Name 0: 0000000000000000 0 NOTYPE LOCAL DEFAULT UND 1: 00000000000a74e0 0 SECTION LOCAL DEFAULT 10 2: 0000000000264180 0 SECTION LOCAL DEFAULT 17 3: 0000000000000000 0 NOTYPE WEAK DEFAULT UND _ITM_addUserCommitAction 4: 0000000000000000 0 NOTYPE WEAK DEFAULT UND _ITM_memcpyRtWn 5: 0000000000000000 0 NOTYPE LOCAL DEFAULT UND readelf: Warning: local symbol 5 found at index >= .dynsym's sh_info value of 3 6: 0000000000000000 0 NOTYPE LOCAL DEFAULT UND readelf: Warning: local symbol 6 found at index >= .dynsym's sh_info value of 3 [snip] This patch removes the symbols from .dynsym too. PR 17550 * elflink.c (_bfd_elf_fix_symbol_flags): Hide dynamic symbols in discarded sections. (cherry picked from commit af0bfb9c)
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Nick Clifton authored
This patch adds support for the SSBB and PSSBB speculation barrier instructions to the AArch64 assembler and disassembler. For more details see: https://static.docs.arm.com/ddi0596/a/DDI_0596_ARM_a64_instruction_set_architecture.pdf opcodes * aarch64-tbl.h (aarch64_opcode_table): Add entry for ssbb and pssbb and update dsb flags to F_HAS_ALIAS. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. gas * testsuite/gas/aarch64/system.s: Add test for ssbb and pssbb. * testsuite/gas/aarch64/system.d: Update accordingly and remove explicit addresses.
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Nick Clifton authored
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Sudakshina Das authored
opcodes * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move csdb together with them. (thumb32_opcodes): Likewise. gas * config/tc-arm.c (insns): Add new ssbb and pssbb instructions. * testsuite/gas/arm/csdb.s: Add new tests for ssbb and pssbb. * testsuite/gas/arm/csdb.d: Likewise * testsuite/gas/arm/thumb2_it_bad.s: Likewise. * testsuite/gas/arm/thumb2_it_bad.l: Likewise. * testsuite/gas/arm/barrier.d: Update with ssbb. * testsuite/gas/arm/barrier-thumb.d: Likewise. -
Tamar Christina authored
This adds the missing Em16 constraints the rest of the instructions requiring them and also adds a testcase to test all the instructions so these are checked from now on. The Em16 operand constrains the valid registers to the lower 16 registers when used with a half precision qualifier. The list has been cross checked (by hand) through the Arm ARM version Ca. opcodes/ PR binutils/23192 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2, mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal, umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull, sqdmulh, sqrdmulh): Use Em16. gas/ PR binutils/23192 * testsuite/gas/aarch64/illegal-by-element.s: New. * testsuite/gas/aarch64/illegal-by-element.d: New. * testsuite/gas/aarch64/illegal-by-element.l: New. (cherry picked from commit 45a28947) Signed-off-by:
Tamar Christina <tamar.christina@arm.com>
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GDB Administrator authored
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- 11 Jul, 2018 5 commits
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Max Filippov authored
Resolved reference to a weak undefined symbol in PIE must not have a dynamic relative relocation against itself, otherwise the value of a reference will be changed from 0 to the base of executable, breaking code like the following: void weak_function (void); if (weak_function) weak_function (); This fixes tests for PR ld/22269 and a number of PIE tests in xtensa gcc testsuite. bfd/ 2018-07-11 Max Filippov <jcmvbkbc@gmail.com> * elf32-xtensa.c (elf_xtensa_allocate_dynrelocs): Don't allocate space for dynamic relocation for undefined weak symbol. (elf_xtensa_relocate_section): Don't emit R_XTENSA_RELATIVE relocation for undefined weak symbols. (shrink_dynamic_reloc_sections): Don't shrink dynamic relocation section for relocations against undefined weak symbols. (cherry picked from commit c451bb34) -
Nick Clifton authored
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Franz Sirl authored
Reimport a patch to fix building gold on Cygwin64 systms: m.arena has size_t on Cygwin64 and thus errors out due to -Werror=format. gold * main.cc: Print m.arena as long long.
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Franz Sirl authored
I just stumbled over this with 2.29.1 while building a cross-toolchain, on Cygwin64, but it's still the same for 2.30. m.arena has size_t on Cygwin64 and thus errors out due to -Werror=format. gold * main.cc: Print m.arena as long long.
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GDB Administrator authored
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- 10 Jul, 2018 3 commits
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Maciej W. Rozycki authored
Remove `-Wshadow' compilation errors: cc1: warnings being treated as errors .../bfd/elflink.c: In function 'bfd_elf_final_link': .../bfd/elflink.c:11722: error: declaration of 'remove' shadows a global declaration /usr/include/stdio.h:154: error: shadowed declaration is here which for versions of GCC before 4.8 prevent support for ELF targets from being built. See also GCC PR c/53066. bfd/ * elflink.c (bfd_elf_final_link): Rename `remove' local variable to `remove_section'. (cherry picked from commit 5270eddc)
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Cary Coutant authored
Testing for the GCC version 5 or later isn't right, since C++ 11 support wasn't enabled by default until later. This patch tests the C++ standard support directly instead of inferring it from the GCC version. gold/ * incremental.cc (Sized_incremental_binary::setup_readers): Use emplace_back for C++ 11 or later.
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GDB Administrator authored
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- 09 Jul, 2018 5 commits
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H.J. Lu authored
There is no need to generate x86 ISA properties with empty bits in linker output. bfd/ PR ld/23372 * elfxx-x86.c (_bfd_x86_elf_merge_gnu_properties): Remove x86 ISA properties with empty bits. ld/ PR ld/23372 * testsuite/ld-i386/i386.exp: Run pr23372a and pr23372b. * testsuite/ld-i386/pr23372a.d: New file. * testsuite/ld-i386/pr23372a.s: Likewise. * testsuite/ld-i386/pr23372b.d: Likewise. * testsuite/ld-i386/pr23372b.s: Likewise. * testsuite/ld-i386/pr23372c.s: Likewise. * testsuite/ld-x86-64/pr23372a-x32.d: Likewise. * testsuite/ld-x86-64/pr23372a.d: Likewise. * testsuite/ld-x86-64/pr23372a.s: Likewise. * testsuite/ld-x86-64/pr23372b-x32.d: Likewise. * testsuite/ld-x86-64/pr23372b.d: Likewise. * testsuite/ld-x86-64/pr23372b.s: Likewise. * testsuite/ld-x86-64/pr23372c.s: Likewise. * testsuite/ld-x86-64/x86-64.exp: Run pr23372a, pr23372a-x32, pr23372b and pr23372b-x32. (cherry picked from commit 56ad703d)
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Alan Modra authored
Fixes a number of build errors like the following .../elf32-arm.c: In function 'elf32_arm_nabi_write_core_note': .../elf32-arm.c:2177: error: #pragma GCC diagnostic not allowed inside functions .../elf32-arm.c:2186: error: #pragma GCC diagnostic not allowed inside functions See the comment in diagnostics.h. include/ * diagnostics.h: Comment on macro usage. bfd/ * elf32-arm.c (elf32_arm_nabi_write_core_note): Don't use DIAGNOTIC_PUSH and DIAGNOSTIC_POP unconditionally. * elf32-ppc.c (ppc_elf_write_core_note): Likewise. * elf32-s390.c (elf_s390_write_core_note): Likewise. * elf64-ppc.c (ppc64_elf_write_core_note): Likewise. * elf64-s390.c (elf_s390_write_core_note): Likewise. * elfxx-aarch64.c (_bfd_aarch64_elf_write_core_note): Likewise. (cherry picked from commit fe75810f)
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Alan Modra authored
elfcpp/ * powerpc.h (Tag_GNU_Power_ABI_FP): Define. (Tag_GNU_Power_ABI_Vector, Tag_GNU_Power_ABI_Struct_Return): Define. gold/ * powerpc.cc: Include attributes.h. (Powerpc_relobj::attributes_section_data_): New variable, with accessor and associated constructor and destructor support. (Powerpc_dynobj::attributes_section_data_): Likewise. (Powerpc_relobj::do_read_symbols): Stash SHT_GNU_ATTRIBUTES section contents in attributes_section_data_. (Powerpc_dynobj::do_read_symbols): Likewise. (Target_powerpc): Add attributes_section_data_, last_fp_, last_ld_, last_vec_, and last_struct_ vars. (Target_powerpc::merge_object_attributes): New function. (Target_powerpc::do_finalize_sections): Iterate over input objects merging attributes. Create output attributes section. (cherry picked from commit 724436fc)
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GDB Administrator authored
- 08 Jul, 2018 1 commit
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GDB Administrator authored
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- 07 Jul, 2018 1 commit
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GDB Administrator authored
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- 06 Jul, 2018 6 commits
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Jim Wilson authored
bfd/ * config.bfd (riscv32*-*-*): Renamed from riscv32-*-*. (riscv64*-*-*): Likewise. (riscv-*-*): Add as an alias for riscv32*-*-*. ld/ * configure.tgt (riscv-*-*): Add as an alias for riscv32*-*-*. (cherry picked from commit bb11866d)
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Tamar Christina authored
The disassembly mask for ldarh incorrectly didn't mask out bit 20 which is part of the SBO part of the instruction and shouldn't be considered input. This fixes the wrong bit fixing the disassembly of instructions to ldarh and makes the behavior consistent. opcodes/ PR binutils/23242 * aarch64-tbl.h (ldarh): Fix disassembly mask. (cherry picked from commit f311ba7e) Signed-off-by:
Tamar Christina <tamar.christina@arm.com>
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Tamar Christina authored
The previous constraints were based on information already in opcodes and it seems that a few of them were wrong. I have now hand verified the ones changed by the previous patch and corrected where needed. This prevents a warning to be issued when one shouldn't be. opcodes/ PR binutils/23369 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1, vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1. gas/testsuite/ PR binutils/23369 * gas/aarch64/msr.d (csselr_el1, vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1): New. * gas/aarch64/msr.s: Likewise. (cherry picked from commit cba05feb) Signed-off-by:
Tamar Christina <tamar.christina@arm.com>
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Nick Clifton authored
* write.c (maybe_generate_build_notes): Bias reloc offsets by the number of notes already generated.
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Sebastian Huber authored
* config.sub: Sync with upstream version 2018-07-03.
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GDB Administrator authored
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