and though bugs are the bane of my existence, rest assured the wretched thing will get the best of care here

  1. 02 Mar, 2017 3 commits
    • Tristan Gingold's avatar
      Add generated files · 7fa39330
      Tristan Gingold authored
      7fa39330
    • Nick Clifton's avatar
      Sync libiberty sources with GCC mainline. · 95e58507
      Nick Clifton authored
      Brings in:
        2017-01-18  Markus Trippelsdorf  <markus@trippelsdorf.de>
      
      	PR PR c++/70182
      	* cp-demangle.c (d_unqualified_name): Handle "on" for
      	operator names.
      	* testsuite/demangle-expected: Add tests.
      
       2017-01-18  Markus Trippelsdorf  <markus@trippelsdorf.de>
      
      	PR c++/77489
      	* cp-demangle.c (d_discriminator): Handle discriminator >= 10.
      	* testsuite/demangle-expected: Add tests for discriminator.
      
       2016-12-13  Jakub Jelinek  <jakub@redhat.com>
      
      	PR c++/78761
      	* cp-demangle.c (cplus_demangle_type): Demangle Dc as decltype(auto).
      	* testsuite/demangle-expected: Add test for decltype(auto).
      95e58507
    • GDB Administrator's avatar
      Automatic date update in version.in · 1b2d1fd5
      GDB Administrator authored
      1b2d1fd5
  2. 01 Mar, 2017 1 commit
  3. 28 Feb, 2017 4 commits
    • Alan Modra's avatar
      Nios2 dynobj handling fixes · cc6b110b
      Alan Modra authored
      A number of places in elf32-nios.c created dynamic sections but didn't
      set the hash table dynobj.  That meant we could have duplicate dynamic
      sections connected to a number of bfds, so size_dynamic_sections
      didn't properly discard or allocate contents.
      
      Also, the entire set of dynamic sections was created in check_relocs
      on seeing GOT relocs, when only .got related sections are needed,
      probably done to hide segfaults later in finish_dynamic_sections.
      
      The patch fixes these issues and makes the assembler emit errors when
      nios2 lacks the necessary pc-relative relocs for subtraction
      expressions, rather than silently generating bad code.
      eg. ld-elf/merge.  I've also tidied uses of elf32_nios2_hash_table and
      elf_hash_table.
      
      bfd/
      	PR 20995
      	* elf32-nios2.c (nios2_elf32_relocate_section): Use htab
      	rather than elf32_nios2_hash_table or elf_hash_table.
      	(create_got_section): Likewise.
      	(nios2_elf32_finish_dynamic_symbol): Likewise.
      	(nios2_elf32_adjust_dynamic_symbol): Likewise.
      	(nios2_elf32_size_dynamic_sections): Likewise.
      	(nios2_elf32_check_relocs): Delete dynobj, sgot, and srelgot
      	vars.  Use htab equivalents directly instead.  Don't create
      	all dynamic sections on needing just the GOT.  Use a goto
      	rather than a fall-through with reloc test.  Ensure
      	htab->dynobj is set when making dynamic sreloc section.
      	(nios2_elf32_finish_dynamic_sections): Delete dynobj, use htab
      	equivalent directly instead.  Don't segfault on looking for
      	.dynamic when dynamic sections have not been created.  Don't
      	segfault on .got.plt being discarded.
      	(nios2_elf32_size_dynamic_sections): Delete plt and got vars.
      	Don't set "relocs" on .rela.plt.  Do handle .sbss.  Delete
      	fixme and another not so relevant comment.
      	(nios2_elf_add_symbol_hook): Delete dynobj var.  If not
      	already set, set hash table dynobj on creating .sbss.
      gas/
      	* config/tc-nios2.h (TC_FORCE_RELOCATION_SUB_LOCAL): Define.
      ld/
      	* testsuite/ld-elf/merge.d: xfail for nios.
      cc6b110b
    • Alan Modra's avatar
      Don't make dynamic .data.rel.ro SEC_READONLY · 3137ed42
      Alan Modra authored
      I'd made this dynamic section read-only so a flag test distinguished
      it from .dynbss, but like any other .data.rel.ro section it really
      should be marked read-write.  (It is read-only after relocation, not
      before.)  When using the standard linker scripts this usually doesn't
      matter since the output section is among other read-write sections and
      not page aligned.  However, it might matter in the extraordinary case
      of the dynamic section being the only .data.rel.ro section with the
      output section just happening to be page aligned and a multiple of a
      page in size.  In that case the output section would be read-only, and
      live it its own read-only PT_LOAD segment, which is incorrect.
      
      	* elflink.c (_bfd_elf_create_dynamic_sections): Don't make
      	dynamic .data.rel.ro read-only.
      	* elf32-arm.c (elf32_arm_finish_dynamic_symbol): Compare section
      	rather than section flags when deciding where copy reloc goes.
      	* elf32-cris.c (elf_cris_finish_dynamic_symbol): Likewise.
      	* elf32-hppa.c (elf32_hppa_finish_dynamic_symbol): Likewise.
      	* elf32-i386.c (elf_i386_finish_dynamic_symbol): Likewise.
      	* elf32-metag.c (elf_metag_finish_dynamic_symbol): Likewise.
      	* elf32-microblaze.c (microblaze_elf_finish_dynamic_symbol): Likewise.
      	* elf32-nios2.c (nios2_elf32_finish_dynamic_symbol): Likewise.
      	* elf32-or1k.c (or1k_elf_finish_dynamic_symbol): Likewise.
      	* elf32-ppc.c (ppc_elf_finish_dynamic_symbol): Likewise.
      	* elf32-s390.c (elf_s390_finish_dynamic_symbol): Likewise.
      	* elf32-tic6x.c (elf32_tic6x_finish_dynamic_symbol): Likewise.
      	* elf32-tilepro.c (tilepro_elf_finish_dynamic_symbol): Likewise.
      	* elf64-ppc.c (ppc64_elf_finish_dynamic_symbol): Likewise.
      	* elf64-s390.c (elf_s390_finish_dynamic_symbol): Likewise.
      	* elf64-x86-64.c (elf_x86_64_finish_dynamic_symbol): Likewise.
      	* elfnn-aarch64.c (elfNN_aarch64_finish_dynamic_symbol): Likewise.
      	* elfnn-riscv.c (riscv_elf_finish_dynamic_symbol): Likewise.
      	* elfxx-mips.c (_bfd_mips_vxworks_finish_dynamic_symbol): Likewise.
      	* elfxx-sparc.c (_bfd_sparc_elf_finish_dynamic_symbol): Likewise.
      	* elfxx-tilegx.c (tilegx_elf_finish_dynamic_symbol): Likewise.
      3137ed42
    • Alan Modra's avatar
      PowerPC addpcis fix · 6ad77d07
      Alan Modra authored
      This came up because I was looking at ld/tmpdir/addpcis.o and noticed
      the odd addends on REL16DX_HA.  They ought to both be -4.  The error
      crept in due REL16DX_HA howto being pc-relative (as indeed it should
      be), and code at gas/write.c:1001 after this comment
      	      /* Make it pc-relative.  If the back-end code has not
      		 selected a pc-relative reloc, cancel the adjustment
      		 we do later on all pc-relative relocs.  */
      *not* cancelling the pc-relative adjustment.  So I've made a dummy
      non-relative split reloc so that the generic code handles this, rather
      than attempting to add hacks later in md_apply_fix which would not be
      very robust.  Having the new internal reloc also makes it easy to
      support
      
       addpcis rx,sym@ha
      
      as an equivalent to
      
       addpcis rx,(sym-0f)@ha
      0:
      
      The patch also fixes overflow checking, which must test whether the
      addi will overflow too since @l relocs don't have any overflow check.
      
      Lastly, since I was poking at md_apply_fix, I arranged to have the
      generic gas/write.c code emit errors for subtraction expressions where
      we lack reloc support.
      
      include/
      	* elf/ppc64.h (R_PPC64_16DX_HA): New.  Expand fake reloc comment.
      	* elf/ppc.h (R_PPC_16DX_HA): Likewise.
      bfd/
      	* reloc.c (BFD_RELOC_PPC_16DX_HA): New.
      	* elf64-ppc.c (ppc64_elf_howto_raw <R_PPC64_16DX_HA>): New howto.
      	(ppc64_elf_reloc_type_lookup): Translate new bfd reloc.
      	(ppc64_elf_ha_reloc): Correct overflow test on REL16DX_HA.
      	(ppc64_elf_relocate_section): Likewise.
      	* elf32-ppc.c (ppc_elf_howto_raw <R_PPC_16DX_HA>): New howto.
      	(ppc_elf_reloc_type_lookup): Translate new bfd reloc.
      	(ppc_elf_check_relocs): Handle R_PPC_16DX_HA to pacify gcc.
      	* libbfd.h: Regenerate.
      	* bfd-in2.h: Regenerate.
      gas/
      	* config/tc-ppc.c (md_assemble): Use BFD_RELOC_PPC_16DX_HA for addpcis.
      	(md_apply_fix): Remove fx_subsy check.  Move code converting to
      	pcrel reloc earlier and handle BFD_RELOC_PPC_16DX_HA.  Remove code
      	emiiting errors on seeing fx_pcrel set on unexpected relocs, as
      	that is done now by the generic code via..
      	* config/tc-ppc.h (TC_FORCE_RELOCATION_SUB_LOCAL): ..this. Define.
      	(TC_VALIDATE_FIX_SUB): Define.
      ld/
      	* testsuite/ld-powerpc/addpcis.d: Define ext1 and ext2 at
      	limits of addpcis range.
      6ad77d07
    • GDB Administrator's avatar
      Automatic date update in version.in · feab5b4b
      GDB Administrator authored
      feab5b4b
  4. 27 Feb, 2017 9 commits
    • Andrew Waterman's avatar
      bfd: RISC-V: relax to gp in more cases. · 6632f6aa
      Andrew Waterman authored
      bfd/ChangeLog:
      
      2017-02-24  Andrew Waterman  <andrew@sifive.com>
      
      	* elfnn-riscv.c (GP_NAME): New macro.
      	(riscv_global_pointer_value): Use it.
      	(_bfd_riscv_relax_lui): If symbol and global pointer are in same
      	output section, consider only that section's alignment.
      6632f6aa
    • Andrew Waterman's avatar
      Add new counter-enable CSRs · 347a7579
      Andrew Waterman authored
      include/ChangeLog:
      
      2017-02-22  Andrew Waterman  <andrew@sifive.com>
      
             * opcode/riscv-opc.h (CSR_SCOUNTEREN): New define.
             (CSR_MCOUNTEREN): Likewise.
             (scounteren): Declare register.
             (mcounteren): Likewise.
      347a7579
    • Andrew Waterman's avatar
      Add SFENCE.VMA instruction · af5d2064
      Andrew Waterman authored
      include/ChangeLog:
      
      2017-02-14  Andrew Waterman  <andrew@sifive.com>
      
              * opcode/riscv-opc.h (MATCH_SFENCE_VMA): New define.
              (MASK_SFENCE_VMA): Likewise.
              (sfence_vma): Declare instruction.
      
      opcodes/ChangeLog:
      
      2017-02-14  Andrew Waterman  <andrew@sifive.com>
      
              * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
              pseudoinstructions.
      af5d2064
    • Richard Sandiford's avatar
      sve · 1e0971e5
      Richard Sandiford authored
      [AArch64] Additional SVE instructions
      
      This patch supports some additions to the SVE architecture prior to
      its public release.
      
      include/
      	* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4x16)
      	(AARCH64_OPND_SVE_IMM_ROT1, AARCH64_OPND_SVE_IMM_ROT2)
      	(AARCH64_OPND_SVE_Zm3_INDEX, AARCH64_OPND_SVE_Zm3_22_INDEX)
      	(AARCH64_OPND_SVE_Zm4_INDEX): New aarch64_opnds.
      
      opcodes/
      	* aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
      	(OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
      	(OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
      	(OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
      	(OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
      	(OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
      	(OP_SVE_V_HSD): New macros.
      	(OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
      	(OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
      	(OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
      	(aarch64_opcode_table): Add new SVE instructions.
      	(aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
      	for rotation operands.  Add new SVE operands.
      	* aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
      	(ins_sve_quad_index): Likewise.
      	(ins_imm_rotate): Split into...
      	(ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
      	* aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
      	(aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
      	functions.
      	(aarch64_ins_sve_addr_ri_s4): New function.
      	(aarch64_ins_sve_quad_index): Likewise.
      	(do_misc_encoding): Handle "MOV Zn.Q, Qm".
      	* aarch64-asm-2.c: Regenerate.
      	* aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
      	(ext_sve_quad_index): Likewise.
      	(ext_imm_rotate): Split into...
      	(ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
      	* aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
      	(aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
      	functions.
      	(aarch64_ext_sve_addr_ri_s4): New function.
      	(aarch64_ext_sve_quad_index): Likewise.
      	(aarch64_ext_sve_index): Allow quad indices.
      	(do_misc_decoding): Likewise.
      	* aarch64-dis-2.c: Regenerate.
      	* aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
      	aarch64_field_kinds.
      	(OPD_F_OD_MASK): Widen by one bit.
      	(OPD_F_NO_ZR): Bump accordingly.
      	(get_operand_field_width): New function.
      	* aarch64-opc.c (fields): Add new SVE fields.
      	(operand_general_constraint_met_p): Handle new SVE operands.
      	(aarch64_print_operand): Likewise.
      	* aarch64-opc-2.c: Regenerate.
      
      gas/
      	* doc/c-aarch64.texi: Document that sve implies fp16, simd and compnum.
      	* config/tc-aarch64.c (parse_vector_type_for_operand): Allow .q
      	to be used with SVE registers.
      	(parse_operands): Handle new SVE operands.
      	(aarch64_features): Make "sve" require F16 rather than FP.  Also
      	require COMPNUM.
      	* testsuite/gas/aarch64/sve.s: Add tests for new instructions.
      	Include compnum tests.
      	* testsuite/gas/aarch64/sve.d: Update accordingly.
      	* testsuite/gas/aarch64/sve-invalid.s: Add tests for new instructions.
      	* testsuite/gas/aarch64/sve-invalid.l: Update accordingly.  Also
      	update expected output for new FMOV and MOV alternatives.
      1e0971e5
    • Richard Sandiford's avatar
      sve · 34578625
      Richard Sandiford authored
      [AArch64] Add a "compnum" feature
      
      This patch adds a named "compnum" feature for the ARMv8.3-A FCADD
      and FCMLA extensions.
      
      include/
      	* opcode/aarch64.h (AARCH64_FEATURE_COMPNUM): New macro.
      	(AARCH64_ARCH_V8_3): Include AARCH64_FEATURE_COMPNUM.
      
      opcodes/
      	* aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
      	(aarch64_feature_compnum): ...this.
      	(SIMD_V8_3): Replace with...
      	(COMPNUM): ...this.
      	(CNUM_INSN): New macro.
      	(aarch64_opcode_table): Use it for the complex number instructions.
      
      gas/
      	* doc/c-aarch64.texi: Add a "compnum" entry.
      	* config/tc-aarch64.c (aarch64_features): Likewise,
      	* testsuite/gas/aarch64/advsimd-compnum.s: New test.
      	* testsuite/gas/aarch64/advsimd-compnum.d: Likewise.
      34578625
    • Richard Sandiford's avatar
      sve · 3829cd97
      Richard Sandiford authored
      [AArch64] Add SVE system registers
      
      This patch adds the SVE-specific system registers.
      
      opcodes/
      	* aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
      	(aarch64_sys_reg_supported_p): Handle them.
      
      gas/
      	* testsuite/gas/aarch64/sve-sysreg.s,
      	testsuite/gas/aarch64/sve-sysreg.d,
      	testsuite/gas/aarch64/sve-sysreg-invalid.d,
      	testsuite/gas/aarch64/sve-sysreg-invalid.l: New tests.
      3829cd97
    • Richard Sandiford's avatar
      sve · 111ebbf9
      Richard Sandiford authored
      [AArch64] Fix +sve documentation
      
      The documentation entry for the SVE feature incorrectly said that
      it was enabled by default for ARMv8-A or later.  This patch fixes
      that and also mentions that +sve implies +simd.  (It also implies
      +fp, but that follows by transitivity.)
      
      gas/
      	* doc/c-aarch64.texi: Fix sve entry.
      111ebbf9
    • Richard Sandiford's avatar
      [AArch64] Add separate feature flag for weaker release consistent load insns · 3843af67
      Richard Sandiford authored
      The weaker release consistency support of ARMv8.3-A is allowed as an optional
      extension for ARMv8.2-A, so separate command line option and feature flag is
      added: -march=armv8.2-a+rcpc turns LDAPR, LDAPRB, LDAPRH instructions on.
      
      opcodes/
      2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
      
      	* aarch64-tbl.h (RCPC, RCPC_INSN): Define.
      	(aarch64_opcode_table): Use RCPC_INSN.
      
      include/
      2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
      
      	* opcode/aarch64.h (AARCH64_FEATURE_RCPC): Define.
      	(AARCH64_ARCH_V8_3): Update.
      
      gas/
      2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
      
      	* config/tc-aarch64.c (aarch64_features): Add rcpc.
      	* doc/c-aarch64.texi (AArch64 Extensions): Document rcpc.
      	* testsuite/gas/aarch64/ldst-exclusive-armv8_3.d: Rename to ...
      	* testsuite/gas/aarch64/ldst-rcpc.d: This.
      	* testsuite/gas/aarch64/ldst-exclusive-armv8_3.s: Rename to ...
      	* testsuite/gas/aarch64/ldst-rcpc.s: This.
      	* testsuite/gas/aarch64/ldst-rcpc-armv8_2.d: New test.
      3843af67
    • GDB Administrator's avatar
      Automatic date update in version.in · 913e8ffc
      GDB Administrator authored
      913e8ffc
  5. 26 Feb, 2017 1 commit
  6. 25 Feb, 2017 1 commit
  7. 24 Feb, 2017 1 commit
  8. 23 Feb, 2017 4 commits
    • Andreas Krebbel's avatar
      S/390: Issue error for overflowing relocs. · 844be12f
      Andreas Krebbel authored
      Building PIE executable from non-PIC code results in broken binaries.
      With this patch the problem is detected at link-time.
      
      bfd/ChangeLog:
      
      2017-01-07  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
      
      	* elf64-s390.c (elf_s390_relocate_section): Issue error for
      	non-PLT relocs of shared libary symbol in exectuable.
      844be12f
    • Andreas Krebbel's avatar
      S/390: Add support for new cpu architecture - arch12. · c7b66f4d
      Andreas Krebbel authored
      This adds support of new instructions to the S/390 specific parts.
      
      The important feature of the new instruction set is the support of
      single and extended precision floating point vector operations.
      
      Note: arch12 is NOT the official name of the new CPU.  It just
      continues the series of archXX options supported as alternate names.
      The archXX terminology refers to the edition number of the Principle
      of Operations manual.  The official CPU name will be added later while
      keeping support of the arch12 for backwards compatibility.
      
      No testsuite regressions.
      
      Committed to mainline.
      
      Bye,
      
      -Andreas-
      
      opcodes/ChangeLog:
      
      2017-02-23  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
      
      	* s390-mkopc.c (main): Accept arch12 as cpu string and vx2 as
      	facility.
      	* s390-opc.c: Add new operand description macros, new instruction
      	types, instruction masks, and new .insn instruction types.
      	* s390-opc.txt: Add new arch12 instructions.
      
      include/ChangeLog:
      
      2017-02-23  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
      
      	* opcode/s390.h (enum s390_opcode_cpu_val): New value
      	S390_OPCODE_ARCH12.
      	(S390_INSTR_FLAG_VX2): New macro definition.
      
      gas/ChangeLog:
      
      2017-02-23  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
      
      	* config/tc-s390.c (s390_parse_cpu): New entry for arch12.
      	* doc/as.texinfo: Document arch12 as cpu type.
      	* doc/c-s390.texi: Likewise.
      	* testsuite/gas/s390/s390.exp: Run arch12 specific tests.
      	* testsuite/gas/s390/zarch-arch12.d: New test.
      	* testsuite/gas/s390/zarch-arch12.s: New test.
      	* testsuite/gas/s390/zarch-z13.d: Rename some mnemonics in the
      	output patterns.
      c7b66f4d
    • Alan Modra's avatar
      Correct VLE 16D and SDAREL relocations · 55ff5228
      Alan Modra authored
      	PR 20744
      bfd/
      	* elf32-ppc.c (ppc_elf_howto_raw): Correct dst_mask on all VLE
      	16D relocations.
      	(ppc_elf_vle_split16): Correct field mask and shift for 16D relocs.
      	(ppc_elf_relocate_section): Correct calculation for VLE SDAREL
      	relocs.
      ld/
      	* testsuite/ld-powerpc/vle-reloc-2.s: Use r6 for last insn of
      	each group.
      	* testsuite/ld-powerpc/vle-reloc-2.d: Update for above change
      	and sdarel reloc fix.
      55ff5228
    • GDB Administrator's avatar
      Automatic date update in version.in · edec15c2
      GDB Administrator authored
      edec15c2
  9. 22 Feb, 2017 1 commit
  10. 21 Feb, 2017 2 commits
    • Alan Modra's avatar
      PowerPC ld segfault on script discarding dynamic sections · 3fd0b4b3
      Alan Modra authored
      bfd/
      	* elf64-ppc.c (ppc64_elf_finish_dynamic_sections): Don't segfault
      	on .got or .plt output section being discarded by script.
      	* elf32-ppc.c (ppc_elf_finish_dynamic_sections): Likewise.  Move
      	vxworks splt temp.
      gold/
      	* powerpc.cc (Target_powerpc::make_iplt_section): Check that
      	output_section exists before attempting add_output_section_data.
      	(Target_powerpc::make_brlt_section): Likewise.
      3fd0b4b3
    • GDB Administrator's avatar
      Automatic date update in version.in · 22b48854
      GDB Administrator authored
      22b48854
  11. 20 Feb, 2017 2 commits
  12. 19 Feb, 2017 1 commit
  13. 18 Feb, 2017 1 commit
  14. 17 Feb, 2017 1 commit
  15. 16 Feb, 2017 6 commits
    • Alan Modra's avatar
      xfail two ld-unique tests for hppa · 0a4cafce
      Alan Modra authored
      HPPA doesn't use OSABI of SYSV.
      
      	* testsuite/ld-unique/unique.exp: xfail two tests for hppa.
      0a4cafce
    • Alan Modra's avatar
      ld testsuite function pointer comparisons vs. hppa · ce697216
      Alan Modra authored
      ld/testsuite/ld-elf/check-ptr-eq.c fails for hppa, since function
      pointers may point at plabels.  It isn't valid to cast two function
      pointers to void* and then compare the void pointers.
      
      	* testsuite/ld-elf/check-ptr-eq.c (check_ptr_eq): Change params
      	from void pointers to function pointers.
      	* testsuite/ld-elf/pr18718.c: Update to suit.
      	* testsuite/ld-elf/pr18720a.c: Update to suit.
      ce697216
    • Alan Modra's avatar
      hppa -z relro again · a2db675b
      Alan Modra authored
      I misunderstood the hppa alias problem.  File offsets of segments need
      to be such that no page is mapped twice with different permissions.
      (Which still seems to me like something the kernel could fix, but
      anyhow, this is not so difficult to achieve in ld.)
      
      	PR 21000
      bfd/
      	* elf-bfd.h (struct elf_backend_data): Add no_page_alias.
      	* elfxx-target.h (elf_backend_no_page_alias): Define.
      	(elfNN_bed): Init new field.
      	* elf.c (assign_file_positions_for_load_sections): If no_page_alias
      	ensure PT_LOAD segment starts on a new page.
      	* elf32-hppa.c (elf_backend_no_page_alias): Define.
      ld/
      	* testsuite/ld-elf/loadaddr1.d: Adjust for hppa file offsets.
      	* testsuite/ld-elf/loadaddr2.d: Likewise.
      	* testsuite/ld-elf/loadaddr3a.d: Likewise.
      	* testsuite/ld-scripts/rgn-at5.d: Likewise.
      a2db675b
    • Alan Modra's avatar
      PR21132, hppa-linux pie support doesn't work · 8a3cacb0
      Alan Modra authored
      This fixes a long-standing hppa bug seen when generating PIEs, and I
      think possible to trigger with forced local symbols in shared
      libraries.  Not allocating enough space for PLT relocs results in ld
      writing outside of the buffer.
      
      	PR 21132
      	* elf32-hppa.c (allocate_plt_static): Allocate space for relocs
      	if pic.
      8a3cacb0
    • Alan Modra's avatar
      Fix more powerpc testsuite source errors · ea988916
      Alan Modra authored
      	* testsuite/ld-powerpc/vxworks1-lib.s: Correct addi to addic.
      	* testsuite/ld-powerpc/vxworks1-lib.dd: Adjust to suit.
      ea988916
    • GDB Administrator's avatar
      Automatic date update in version.in · 978e81fd
      GDB Administrator authored
      978e81fd
  16. 15 Feb, 2017 2 commits
    • H.J. Lu's avatar
      i386: Allow "lea foo@GOT, %reg" in PIC · 531ecb82
      H.J. Lu authored
      "lea foo@GOT, %reg" is OK in PIC since it only loads the GOT offset
      into register, which can be used later with a GOT base register to
      get the value in the GOT entry.
      
      (cherry picked from commit 2a568401)
      
      bfd/
      
      	PR ld/21168
      	* elf32-i386.c (elf_i386_relocate_section): Allow
      	"lea foo@GOT, %reg" in PIC.
      
      ld/
      
      	PR ld/21168
      	* testsuite/ld-i386/i386.exp: Run pr21168.
      	* testsuite/ld-i386/pr21168a.c: New file.
      	* testsuite/ld-i386/pr21168b.S: Likewise.
      531ecb82
    • GDB Administrator's avatar
      Automatic date update in version.in · 82f83aa4
      GDB Administrator authored
      82f83aa4