- 21 Jul, 2015 2 commits
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Tristan Gingold authored
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GDB Administrator authored
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- 20 Jul, 2015 1 commit
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GDB Administrator authored
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- 19 Jul, 2015 1 commit
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GDB Administrator authored
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- 18 Jul, 2015 1 commit
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GDB Administrator authored
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- 17 Jul, 2015 1 commit
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GDB Administrator authored
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- 16 Jul, 2015 2 commits
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Alan Modra authored
PR binutils/18672 * readelf.c (get_32bit_dynamic_section): Correct buffer limit test. (get_64bit_dynamic_section): Likewise.
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GDB Administrator authored
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- 15 Jul, 2015 1 commit
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GDB Administrator authored
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- 14 Jul, 2015 1 commit
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GDB Administrator authored
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- 13 Jul, 2015 1 commit
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GDB Administrator authored
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- 12 Jul, 2015 1 commit
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GDB Administrator authored
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- 11 Jul, 2015 1 commit
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GDB Administrator authored
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- 10 Jul, 2015 16 commits
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Richard Sandiford authored
bfd/ * elf64-ppc.c (toc_adjusting_stub_needed): Use the symbol value plus addend rather than the original st_value when looking up entries in opd->adjust. ld/testsuite/ * ld-powerpc/tocopt6-inc.s, ld-powerpc/tocopt6a.s, ld-powerpc/tocopt6b.s, ld-powerpc/tocopt6c.s, ld-powerpc/tocopt6.d: New test. * ld-powerpc/powerpc.exp (ppc64elftests): Add it.
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Alan Modra authored
Back in the day support for these processors was added, we probably didn't want to waste PPC_OPCODE bits on minor variations. I've had a complaint that disassembly of mfspr/mtspr was wrong for power8. This patch fixes that problem. Note that since -m860/-m850/-m821 are new gas options enabling the mpc8xx specific mfspr/mtspr variants it is possible that this change will break some mpc8xx assembly code. ie. you might need to modify makefiles to pass -m860 to gas. include/opcode/ * ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define. opcodes/ * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*. * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry. gas/ * config/tc-ppc.c (md_show_usage): Add -m821, -m850, -m860. * doc/c-ppc.texi (PowerPC-Opts): Likewise. gas/testsuite/ * gas/ppc/titan.d: Correct mfmcsrr0 disassembly.
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Peter Bergner authored
ISA 2.07 added a new category called Elemental Memory Barriers that modifies the sync instruction to accept an additional operand ESYNC. Edmar added support for this insruction varient here: https://sourceware.org/ml/binutils/2012-02/msg00221.html Looking at this closer, I see that the insert_ls() function is misnamed (since it's attached to the ESYNC operand, not the LS operand) but more importantly, it is silently modifying the LS operand value behind the users back when the LS operand is either invalid or is incompatible with the new ESYNC operand. The ISA 2.07 doc has an Assembler Note that clearly states that assemblers that support the ESYNC operand should report all invalid uses of LS and ESYNC. This patch changes the assembler to error out on invalid and incompatible operand usage. opcodes/ * ppc-opc.c (insert_ls): Test for invalid LS operands. (insert_esync): New function. (LS, WC): Use insert_ls. (ESYNC): Use insert_esync. gas/testsuite/ * gas/ppc/e6500.s <sync>: Fix invalid test. * gas/ppc/e6500.d: Likewise. -
Peter Bergner authored
ISA 2.07 (ie, POWER8) added the rfebb instruction which takes one operand with the value of either a 0 or 1. It also defines an extended mnemonic with no operands (ie, "rfebb") that is supposed to be equivalent to "rfebb 1". I implemented rfebb's lone operand with PPC_OPERAND_OPTIONAL, but the problem is, optional operands that are ommitted always default to the value 0, which is wrong in this case. I have added support for allowing non-zero default values by adding an additional flag PPC_OPERAND_OPTIONAL_VALUE that specifies that the default operand value to be used is stored in the SHIFT field of the operand field immediately following this one. This fixes the rfebb issue. I also fixed the mftb and mfcr instructions so they use the same mechanism. This allows us to flag invalid uses of mfcr where we explicitly pass in a zero FXM value, like the use in a2.[sd]. include/opcode/ * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New. (ppc_optional_operand_value): New inline function. opcodes/ * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value. * ppc-opc.c (FXM4): Add non-zero optional value. (TBR): Likewise. (SXL): Likewise. (insert_fxm): Handle new default operand value. (extract_fxm): Likewise. (insert_tbr): Likewise. (extract_tbr): Likewise. gas/ * config/tc-ppc.c (md_assemble): Use ppc_optional_operand_value. Allow for optional operands without insert functions. gas/testsuite/ * gas/ppc/power8.d: Fixup rfebb test results. * gas/ppc/a2.s: Fix invalid mfcr test. * gas/ppc/a2.d: Likewise.
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Alan Modra authored
Huh, I can't even write a binary search properly. bfd/ * elf32-ppc.c (ppc_elf_relocate_section): Correct binary search of dynamic relocs. ld/testsuite/ * ld-powerpc/ppc476-shared.s: Repeat dynamic reloc generating insns. * ld-powerpc/ppc476-shared.d: Update. * ld-powerpc/ppc476-shared2.d: Update.
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Peter Bergner authored
In the commit that added PowerPC Pair Singles, Ben accidentally removed a comment and re-added an unused MTMSRD_L macro Alan had recently deleted. This was probably just an oversite when he was refreshing his patch to trunk. opcodes/ * ppc-opc.c: Add comment accidentally removed by old commit. (MTMSRD_L): Delete.
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Alan Modra authored
When building a shared lib from non-PIC objects, we'll get dynamic text relocations. These need to move with any insns we move. Otherwise the dynamic reloc will modify the branch, resulting in crashes and other unpleasant behaviour. Also, ld -r --ppc476-workaround used with sufficiently aligned PIC objects needs a fix for emitted REL16 relocs. bfd/ * elf64-ppc.c (ppc_elf_relocate_section): Move dynamic text relocs with insns moved by --ppc476-workaround. Correct output of REL16 relocs. ld/testsuite/ * ld-powerpc/ppc476-shared.s, * ld-powerpc/ppc476-shared.lnk, * ld-powerpc/ppc476-shared.d, * ld-powerpc/ppc476-shared2.d: New tests. * ld-powerpc/powerpc.exp: Run them.
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Peter Bergner authored
This commit adds a new extended menmonic for "sync 0" (same as "sync"). The ISA documentation doesn't explicitly mention hwsync as an extended mnemonic (yet), but it does mention "heavyweight sync" and "hwsync" as the operation that gets performed when the sync's L field is 0. This is only enabled for POWER4 and later. opcodes/ * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic. gas/testsuite/ * gas/ppc/a2.d: Fixup test case due to new extended mnemonic. * gas/ppc/power4.s <hwsync, lwsync, ptesync, sync>: Add tests. * gas/ppc/power4.d: Likewise.
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Alan Modra authored
Taking them out showed a bug in the powerpc64 backend with .branch_lt being removed from output_bfd but not from previously set up segment section maps. Removing the bfd sections meant their sh_flags (and practically everything else) remaining zero, ie. not SHF_ALLOC, triggering complaints about "`.branch_lt' can't be allocated in segment". include/elf/ * internal.h (ELF_SECTION_IN_SEGMENT_1): Ensure PT_LOAD and similar segments only contain alloc sections. ld/ * emultempl/ppc64elf.em (gld${EMULATION_NAME}_after_allocation): Call gld${EMULATION_NAME}_map_segments regardless of need_laying_out. -
Alan Modra authored
This change, with prerequisite 0e5fabeb, provides a toc base aligned to 256 bytes rather than 8 bytes. This is necessary for a minor gcc optimisation, allowing use of d-form instructions to correctly access toc-relative items larger than 8 bytes. bfd/ * elf64-ppc.c (TOC_BASE_ALIGN): Define. (ppc64_elf_next_toc_section): Align multi-got toc base. (ppc64_elf_set_toc): Likewise initial toc base and .TOC. symbol. ld/ * emulparams/elf64ppc.sh (GOT): Align. ld/testsuite/ * ld-powerpc/ambiguousv1.d: Update for aligned .got. * ld-powerpc/ambiguousv1b.d: Likewise. * ld-powerpc/ambiguousv2.d: Likewise. * ld-powerpc/defsym.d: Likewise. * ld-powerpc/elfv2-2exe.d: Likewise. * ld-powerpc/elfv2exe.d: Likewise. * ld-powerpc/elfv2so.d: Likewise. * ld-powerpc/relbrlt.d: Likewise. * ld-powerpc/tls.g: Likewise. * ld-powerpc/tlsexe.d: Likewise. * ld-powerpc/tlsexe.g: Likewise. * ld-powerpc/tlsexe.r: Likewise. * ld-powerpc/tlsexetoc.d: Likewise. * ld-powerpc/tlsexetoc.g: Likewise. * ld-powerpc/tlsexetoc.r: Likewise. * ld-powerpc/tlsso.d: Likewise. * ld-powerpc/tlsso.g: Likewise. * ld-powerpc/tlsso.r: Likewise. * ld-powerpc/tlstoc.g: Likewise. * ld-powerpc/tlstocso.d: Likewise. * ld-powerpc/tlstocso.g: Likewise. * ld-powerpc/tlstocso.r: Likewise. * ld-powerpc/tocopt.d: Likewise. * ld-powerpc/tocopt2.d: Likewise. * ld-powerpc/tocopt3.d: Likewise. * ld-powerpc/tocopt4.d: Likewise. * ld-powerpc/tocopt5.d: Likewise.
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Alan Modra authored
The linker tries to put the end of the last section in the relro segment exactly on a page boundary, because the relro segment itself must end on a page boundary. If for any reason this can't be done, padding is inserted. Since the end of the relro segment is typically between .got and .got.plt, padding effectively increases the size of the GOT. This isn't nice for targets and code models with limited GOT addressing. The problem with the current code is that it doesn't cope very well with aligned sections in the relro segment. When making .got aligned to a 256 byte boundary for PowerPC64, I found that often the initial alignment attempt failed and the fallback attempt to be less than adequate. This is a particular problem for PowerPC64 since the distance between .got and .plt affects the size of plt call stubs, leading to "stubs don't match calculated size" errors. So this rewrite takes a direct approach to calculating a new relro base. Starting from the last section in the segment, we calculate where it must start to position its end on the boundary, or as near as possible considering alignment requirements. The new start then becomes the goal for the previous section to end, and so on for all sections. This of course ignores the possibility that user scripts will place . = ALIGN(xxx); in the relro segment, or provide section address expressions. In those cases we might fail, but the old code probably did too, and a fallback is provided. ld/ * ldexp.h (struct ldexp_control): Delete dataseg.min_base. Add data_seg.relro_offset. * ldexp.c (fold_binary <DATA_SEGMENT_ALIGN>): Don't set min_base. (fold_binary <DATA_SEGMENT_RELRO_END>): Do set relro_offset. * ldlang.c (lang_size_sections): Rewrite code adjusting relro segment base to line up last section on page boundary.
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Anton Blanchard authored
The gdb TUI is calling gdb_print_insn() (which calls disassemble_init_powerpc()) enough to show up high in profiles. As suggested by Alan, only initialise if the indices are empty. * ppc-dis.c (disassemble_init_powerpc): Only initialise powerpc_opcd_indices and vle_opcd_indices once.
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Anton Blanchard authored
* ppc-opc.c (powerpc_opcodes): Add slbfee.
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Alan Modra authored
* elf64-ppc.c (ppc64_elf_relocate_section): Report overflow to stubs, even those for undefined weak symbols. Otherwise, don't report relocation overflow on branches to undefined strong symbols. Fix memory leak. * elf32-ppc.c (ppc_elf_relocate_section): Don't report relocation overflow on branches to undefined strong symbols.
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Alan Modra authored
* config/tc-ppc.c (md_assemble): Don't abort on 8 byte insn fixups. (md_apply_fix): Report an error on data-only fixups used with insns.
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GDB Administrator authored
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- 09 Jul, 2015 1 commit
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GDB Administrator authored
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- 08 Jul, 2015 1 commit
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GDB Administrator authored
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- 07 Jul, 2015 2 commits
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Doug Kwan authored
Apply from master 2015-06-29 Doug Kwan <dougkwan@google.com> * testsuite/arm_bl_out_of_range.s: Align stub table so that it appears at address expected by test. * testsuite/arm_cortex_a8_b.s: Ditto. * testsuite/arm_cortex_a8_b_cond.s: Ditto. * testsuite/arm_cortex_a8_bl.s: Ditto. * testsuite/arm_cortex_a8_blx.s: Ditto. * testsuite/arm_cortex_a8_local.s: Ditto. * testsuite/arm_fix_v4bx.s: Ditto. * testsuite/arm_unaligned_reloc.s: Ditto. * testsuite/thumb_bl_out_of_range.s: Ditto. * testsuite/thumb_bl_out_of_range_local.s: Ditto. * testsuite/thumb_blx_out_of_range.s: Ditto.
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GDB Administrator authored
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- 06 Jul, 2015 1 commit
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GDB Administrator authored
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- 05 Jul, 2015 1 commit
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GDB Administrator authored
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- 04 Jul, 2015 1 commit
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GDB Administrator authored
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- 03 Jul, 2015 1 commit
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GDB Administrator authored
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- 02 Jul, 2015 1 commit
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GDB Administrator authored
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- 01 Jul, 2015 1 commit
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GDB Administrator authored
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- 30 Jun, 2015 1 commit
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GDB Administrator authored
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