and though bugs are the bane of my existence, rest assured the wretched thing will get the best of care here

  1. 31 Oct, 2017 1 commit
  2. 26 Oct, 2017 1 commit
  3. 25 Oct, 2017 1 commit
    • Tom Stellard's avatar
      Merging r315485: · 831f8318
      Tom Stellard authored
      ```---------------------------------------------------------------------
      r315485 | spatel | 2017-10-11 11:24:21 -0700 (Wed, 11 Oct 2017) | 7 lines
      
      [x86] avoid infinite loop from SoftenFloatOperand (PR34866)
      
      Legalization of fp128 assumes things that we should have asserts for,
      so that's another potential improvement.
      
      Differential Revision: https://reviews.llvm.org/D38771
      ```
      
      ---------------------------------------------------------------------
      
      llvm-svn: 316607
      831f8318
  4. 14 Oct, 2017 5 commits
    • Dylan McKay's avatar
      Merging r314898: · 5945e5f2
      Dylan McKay authored
      ```---------------------------------------------------------------------
      r314898 | dylanmckay | 2017-10-04 23:37:22 +1300 (Wed, 04 Oct 2017) | 6 lines
      
      [AVR] Implement LPMWRdZ pseudo-instruction's expansion.
      
      FIXME: implementation is mostly copy-pasted from LDWRdPtr, so we should
      refactor a bit and unify the two
      
      Patch by Gerdo Erdi.
      ```
      
      ---------------------------------------------------------------------
      
      llvm-svn: 315836
      5945e5f2
    • Dylan McKay's avatar
      Merging r314897: · c201f241
      Dylan McKay authored
      ```---------------------------------------------------------------------
      r314897 | dylanmckay | 2017-10-04 23:36:07 +1300 (Wed, 04 Oct 2017) | 3 lines
      
      [AVR] Factor out mayLoad in tablegen patterns
      
      Patch by Gergo Erdi.
      ```
      
      ---------------------------------------------------------------------
      
      llvm-svn: 315835
      c201f241
    • Dylan McKay's avatar
      Merging r314896: · fb12e5f4
      Dylan McKay authored
      ```---------------------------------------------------------------------
      r314896 | dylanmckay | 2017-10-04 23:33:36 +1300 (Wed, 04 Oct 2017) | 3 lines
      
      [AVR] Elaborate LDWRdPtr into `ld r, X++; ld r+1, X`
      
      Patch by Gergo Erdi.
      ```
      
      ---------------------------------------------------------------------
      
      llvm-svn: 315834
      fb12e5f4
    • Dylan McKay's avatar
      Merging r314891: · 037e4e65
      Dylan McKay authored
      ```---------------------------------------------------------------------
      r314891 | dylanmckay | 2017-10-04 22:51:28 +1300 (Wed, 04 Oct 2017) | 8 lines
      
      [AVR] Insert JMP for long branches
      
      Previously, on long branches (relative jumps of >4 kB), an assertion
      failure was hit, as AVRInstrInfo::insertIndirectBranch was not
      implemented. Despite its name, it is called by the branch relaxator
      for *all* unconditional jumps.
      
      Patch by Thomas Backman.
      ```
      
      ---------------------------------------------------------------------
      
      llvm-svn: 315833
      037e4e65
    • Dylan McKay's avatar
      Merging r314890: · a8575044
      Dylan McKay authored
      ```---------------------------------------------------------------------
      r314890 | dylanmckay | 2017-10-04 22:51:21 +1300 (Wed, 04 Oct 2017) | 16 lines
      
      [AVR] Fix displacement overflow for LDDW/STDW
      
      In some cases, the code generator attempts to generate instructions such as:
      
      lddw r24, Y+63
      
      which expands to:
      
      ldd r24, Y+63
      ldd r25, Y+64 # Oops! This is actually ld r25, Y in the binary
      
      This commit limits the first offset to 62, and thus the second to 63.
      It also updates some asserts in AVRExpandPseudoInsts.cpp, including for
      INW and OUTW, which appear to be unused.
      
      Patch by Thomas Backman.
      ```
      
      ---------------------------------------------------------------------
      
      llvm-svn: 315832
      a8575044
  5. 13 Oct, 2017 1 commit
    • Tom Stellard's avatar
      Merging r312357: · feff932b
      Tom Stellard authored
      ```---------------------------------------------------------------------
      r312357 | davide | 2017-09-01 12:54:08 -0700 (Fri, 01 Sep 2017) | 9 lines
      
      [TTI] Fix getGEPCost() for geps with a single operand.
      
      Previously this would sporadically crash as TargetType
      was never initialized. We special-case the single-operand
      case returning earlier and trying to mimic the behaviour of
      isLegalAddressingMode as closely as possible.
      
      Differential Revision:  https://reviews.llvm.org/D37277
      ```
      
      ---------------------------------------------------------------------
      
      llvm-svn: 315663
      feff932b
  6. 10 Oct, 2017 1 commit
    • Tom Stellard's avatar
      Merging r314513: · 7aaddf65
      Tom Stellard authored
      ```---------------------------------------------------------------------
      r314513 | hahnfeld | 2017-09-29 06:53:03 -0700 (Fri, 29 Sep 2017) | 3 lines
      
      [test] Fix uninitialized memory in omp_taskloop_grainsize.c
      
      result was never initialized to zero which sometimes failed the test.
      ```
      
      ---------------------------------------------------------------------
      
      llvm-svn: 315353
      7aaddf65
  7. 09 Oct, 2017 1 commit
    • Tom Stellard's avatar
      Merging r309979: · e97b489f
      Tom Stellard authored
      ```---------------------------------------------------------------------
      r309979 | mgorny | 2017-08-03 12:41:33 -0700 (Thu, 03 Aug 2017) | 16 lines
      
      [test] Fix clang library dir in LD_LIBRARY_PATH For stand-alone build
      
      Prepend the clang library directory (determined using SHLIBDIR, alike
      in clang) to the LD_LIBRARY_PATH to ensure that just-built clang
      libraries will be used instead of a previous installed version.
      
      When a stand-alone build is performed, LLVM_LIBS_DIR contains the path
      to installed LLVM library directory. The same directory frequently
      contains a previously installed version of clang. SHLIBDIR, on the other
      hand, is always the build-tree directory, and therefore contains
      the freshly built clang libraries.
      
      In a non-stand-alone build, both paths will be the same and therefore
      including them both will not cause any issues.
      
      Differential Revision: https://reviews.llvm.org/D30155
      ```
      
      ---------------------------------------------------------------------
      
      llvm-svn: 315224
      e97b489f
  8. 08 Oct, 2017 1 commit
    • Craig Topper's avatar
      Merging r313366: · 9fd74c16
      Craig Topper authored
      ```---------------------------------------------------------------------
      r313366 | ctopper | 2017-09-15 10:09:03 -0700 (Fri, 15 Sep 2017) | 9 lines
      
      [X86] Don't create i64 constants on 32-bit targets when lowering v64i1 constant build vectors
      
      When handling a v64i1 build vector of constants on 32-bit targets we were creating an illegal i64 constant that we then bitcasted back to v64i1. We need to instead create two 32-bit constants, bitcast them to v32i1 and concat the result. We should also take care to handle the halves being all zeros/ones after the split.
      
      This patch splits the build vector and then recursively lowers the two pieces. This allows us to handle the all ones and all zeros cases with minimal effort. Ideally we'd just do the split and concat, and let lowering get called again on the new nodes, but getNode has special handling for CONCAT_VECTORS that reassembles the pieces back into a single BUILD_VECTOR. Hopefully the two temporary BUILD_VECTORS we had to create to do this that don't get returned don't cause any issues.
      
      Fixes PR34605.
      
      Differential Revision: https://reviews.llvm.org/D37858
      ```
      
      ---------------------------------------------------------------------
      
      llvm-svn: 315198
      9fd74c16
  9. 04 Oct, 2017 2 commits
    • Dylan McKay's avatar
      Revert r314892 · 542b004d
      Dylan McKay authored
      It was accidentally merged.
      
      llvm-svn: 314893
      542b004d
    • Dylan McKay's avatar
      Merging r314891: · 6b0b442e
      Dylan McKay authored
      ```---------------------------------------------------------------------
      r314891 | dylanmckay | 2017-10-04 22:51:28 +1300 (Wed, 04 Oct 2017) | 8 lines
      
      [AVR] Insert JMP for long branches
      
      Previously, on long branches (relative jumps of >4 kB), an assertion
      failure was hit, as AVRInstrInfo::insertIndirectBranch was not
      implemented. Despite its name, it is called by the branch relaxator
      for *all* unconditional jumps.
      
      Patch by Thomas Backman.
      ```
      
      ---------------------------------------------------------------------
      
      llvm-svn: 314892
      6b0b442e
  10. 03 Oct, 2017 3 commits
    • Rui Ueyama's avatar
      Merging r312706: · 08de6a4a
      Rui Ueyama authored
      ```---------------------------------------------------------------------
      r312706 | anng | 2017-09-07 01:43:56 -0700 (Thu, 07 Sep 2017) | 14 lines
      
      [LLD] Fix padding of .eh_frame when in executable segment
      
      The default padding for an executable segment is the target trap
      instruction which for x86_64 is 0xCC. However, the .eh_frame section
      requires the padding to be zero. The code that writes the .eh_frame
      section assumes that its segment is zero initialized and does not
      explicitly write the zero padding. This does not work when the .eh_frame
      section is in the executable segment (for example when using
      -no-rosegment).
      
      This patch changes the .eh_frame writing code to explicitly write the
      zero padding.
      
      Differential Revision: https://reviews.llvm.org/D37462
      ```
      
      ---------------------------------------------------------------------
      
      llvm-svn: 314861
      08de6a4a
    • Rui Ueyama's avatar
      Merging r313741: · a4fcc49a
      Rui Ueyama authored
      ```---------------------------------------------------------------------
      r313741 | grimar | 2017-09-20 02:27:41 -0700 (Wed, 20 Sep 2017) | 9 lines
      
      [ELF] - Fix segfault when processing .eh_frame.
      
      Its a PR34648 which was a segfault that happened because
      we stored pointers to elements in DenseMap. 
      When DenseMap grows such pointers are invalidated.
      Solution implemented is to keep elements by pointer
      and not by value.
      
      Differential revision: https://reviews.llvm.org/D38034
      ```
      
      ---------------------------------------------------------------------
      
      llvm-svn: 314860
      a4fcc49a
    • Renato Golin's avatar
      [release_50] Merging r313916 · 08d41dde
      Renato Golin authored
      [AArch64] Fix bug in store of vector 0 DAGCombine.
      
      Summary:
      Avoid using XZR/WZR directly as operands to split stores of zero
      vectors.  Doing so can lead to the XZR/WZR being used by an instruction
      that doesn't allow it (e.g. add).
      
      Fixes bug 34674.
      
      Reviewers: t.p.northover, efriedma, MatzeB
      
      Subscribers: aemerson, rengolin, javed.absar, mcrosier, eraman, llvm-commits, kristof.beyls
      
      Differential Revision: https://reviews.llvm.org/D38146
      
      PR34695.
      
      llvm-svn: 314796
      08d41dde
  11. 29 Sep, 2017 6 commits
    • Tom Stellard's avatar
      Merging r313392: · 84c46fba
      Tom Stellard authored
      ```---------------------------------------------------------------------
      r313392 | ctopper | 2017-09-15 13:27:59 -0700 (Fri, 15 Sep 2017) | 7 lines
      
      [X86] Disable _mm512_maskz_set1_epi64 intrinsic on 32-bit targets to prevent a backend isel failure.
      
      The __builtin_ia32_pbroadcastq512_mem_mask we were previously trying to use in 32-bit mode is not implemented in the x86 backend and causes isel to fail in release builds. In debug builds it fails even earlier during legalization with an llvm_unreachable.
      
      While there add the missing test case for this intrinsic for this for 64-bit mode.
      
      This fixes PR34631. D37668 should be able to recover this for 32-bit mode soon. But I wanted to fix the crash ahead of that.
      ```
      
      ---------------------------------------------------------------------
      
      llvm-svn: 314569
      84c46fba
    • Tom Stellard's avatar
      Merging r311951 and r312038: · dead2486
      Tom Stellard authored
      ```---------------------------------------------------------------------
      r311951 | adrian | 2017-08-28 16:07:43 -0700 (Mon, 28 Aug 2017) | 6 lines
      
      Fix a logic error in DwarfExpression::addMachineReg()
      
      This fixes PR34323 and thus splitting undescribable registers into
      smaller, describable sub-registers.
      
      https://bugs.llvm.org/show_bug.cgi?id=34323
      ```
      
      ---------------------------------------------------------------------
      
      ------------------------------------------------------------------------
      r312038 | joerg | 2017-08-29 14:18:07 -0700 (Tue, 29 Aug 2017) | 2 lines
      
      Simplify test case, so that it works for both trunk and release-5.0.
      
      ------------------------------------------------------------------------
      
      llvm-svn: 314567
      dead2486
    • Tom Stellard's avatar
      Merging r312348: · 1c536006
      Tom Stellard authored
      ```---------------------------------------------------------------------
      r312348 | matze | 2017-09-01 11:36:26 -0700 (Fri, 01 Sep 2017) | 39 lines
      
      LiveIntervalAnalysis: Fix alias regunit reserved definition
      
      A register in CodeGen can be marked as reserved: In that case we
      consider the register always live and do not use (or rather ignore)
      kill/dead/undef operand flags.
      
      LiveIntervalAnalysis however tracks liveness per register unit (not per
      register). We already needed adjustments for this in r292871 to deal
      with super/sub registers. However I did not look at aliased register
      there. Looking at ARM:
      
      FPSCR (regunits FPSCR, FPSCR~FPSCR_NZCV) aliases with FPSCR_NZCV
      (regunits FPSCR_NZCV, FPSCR~FPSCR_NZCV) hence they share a register unit
      (FPSCR~FPSCR_NZCV) that represents the aliased parts of the registers.
      This shared register unit was previously considered non-reserved,
      however given that we uses of the reserved FPSCR potentially violate
      some rules (like uses without defs) we should make FPSCR~FPSCR_NZCV
      reserved too and stop tracking liveness for it.
      
      This patch:
      - Defines a register unit as reserved when: At least for one root
        register, the root register and all its super registers are reserved.
      - Adjust LiveIntervals::computeRegUnitRange() for new reserved
        definition.
      - Add MachineRegisterInfo::isReservedRegUnit() to have a canonical way
        of testing.
      - Stop computing LiveRanges for reserved register units in HMEditor even
        with UpdateFlags enabled.
      - Skip verification of uses of reserved reg units in the machine
        verifier (this usually didn't happen because there would be no cached
        liverange but there is no guarantee for that and I would run into this
        case before the HMEditor tweak, so may as well fix the verifier too).
      
      Note that this should only affect ARMs FPSCR/FPSCR_NZCV registers today;
      aliased registers are rarely used, the only other cases are hexagons
      P0-P3/P3_0 and C8/USR pairs which are not mixing reserved/non-reserved
      registers in an alias.
      
      Differential Revision: https://reviews.llvm.org/D37356
      ```
      
      ---------------------------------------------------------------------
      
      llvm-svn: 314565
      1c536006
    • Tom Stellard's avatar
      Merging r314252: · ed5c0ab4
      Tom Stellard authored
      ```---------------------------------------------------------------------
      r314252 | gberry | 2017-09-26 14:40:46 -0700 (Tue, 26 Sep 2017) | 12 lines
      
      [AArch64][Falkor] Fix bug in falkor prefetcher fix pass.
      
      Summary:
      In rare cases, loads that don't get prefetched that were marked as
      strided loads could cause a crash if they occurred in a loop with other
      colliding loads.
      
      Reviewers: mcrosier
      
      Subscribers: aemerson, rengolin, javed.absar, kristof.beyls
      
      Differential Revision: https://reviews.llvm.org/D38261
      ```
      
      ---------------------------------------------------------------------
      
      llvm-svn: 314555
      ed5c0ab4
    • Tom Stellard's avatar
      Merging r314251: · 7507fd1c
      Tom Stellard authored
      ```---------------------------------------------------------------------
      r314251 | gberry | 2017-09-26 14:40:41 -0700 (Tue, 26 Sep 2017) | 16 lines
      
      [AArch64][Falkor] Fix correctness bug in falkor prefetcher fix pass and correct some opcode tag computations.
      
      Summary:
      This addresses a correctness bug for LD[1234]*_POST opcodes that have
      the prefetcher fix applied to them: the base register was not being
      written back from the temp after being incremented, so it would appear
      to never be incremented.
      
      Also, fix some opcode tag computations based on some updated HW details
      to get better tag avoidance and thus better prefetcher performance.
      
      Reviewers: mcrosier
      
      Subscribers: aemerson, rengolin, javed.absar, kristof.beyls
      
      Differential Revision: https://reviews.llvm.org/D38256
      ```
      
      ---------------------------------------------------------------------
      
      llvm-svn: 314554
      7507fd1c
    • Tom Stellard's avatar
      Merging r311599: · 4041da7a
      Tom Stellard authored
      ```---------------------------------------------------------------------
      r311599 | gberry | 2017-08-23 14:11:28 -0700 (Wed, 23 Aug 2017) | 4 lines
      
      [AArch64][Falkor] Fix bug in Falkor HWPF tag collision avoidance
      
      LDPDi was incorrectly marked as ignoring the destination register in the
      prefetcher tag.
      ```
      
      ---------------------------------------------------------------------
      
      llvm-svn: 314553
      4041da7a
  12. 28 Sep, 2017 9 commits
    • Tom Stellard's avatar
      Merging r312447: · afaf2961
      Tom Stellard authored
      ```---------------------------------------------------------------------
      r312447 | hfinkel | 2017-09-03 10:18:25 -0700 (Sun, 03 Sep 2017) | 12 lines
      
      [CodeGen] Treat all vector fields as mayalias
      
      Because it is common to treat vector types as an array of their elements, or
      even some other type that's not the element type, and thus index into them, we
      can't use struct-path TBAA for these accesses. Even though we already treat all
      vector types as equivalent to 'char', we were using field-offset information
      for them with TBAA, and this renders undefined the intra-value indexing we
      intend to allow. Note that, although 'char' is universally aliasing, with path
      TBAA, we can still differentiate between access to s.a and s.b in
        struct { char a, b; } s;. We can't use this capability as-is for vector types.
      
      Fixes PR33967.
      ```
      
      ---------------------------------------------------------------------
      
      llvm-svn: 314476
      afaf2961
    • Tom Stellard's avatar
      Merging r312651: · 3c3efb4e
      Tom Stellard authored
      ```---------------------------------------------------------------------
      r312651 | jroelofs | 2017-09-06 10:09:25 -0700 (Wed, 06 Sep 2017) | 23 lines
      
      Fix ARM bare metal driver to support atomics
      
      The new bare metal support only supports the single thread model. This causes
      the builtin atomic functions (e.g.: __atomic_fetch_add) to not generate
      thread-safe assembly for these operations, which breaks our firmware. We target
      bare metal, and need to atomically modify variables in our interrupt routines,
      and task threads.
      
      Internally, the -mthread-model flag determines whether to lower or expand
      atomic operations (see D4984).
      
      This change removes the overridden thread model methods, and instead relies on
      the base ToolChain class to validate the thread model (which already includes
      logic to validate single thread model support). If the single thread model is
      required, the -mthread-model flag will have to be provided.
      
      As a workaround "-mthread-model posix" could be provided, but it only works due
      to a bug in the validation of the -mthread-model flag (separate patch coming to
      fix this).
      
      https://reviews.llvm.org/D37493
      
      Patch by: Ian Tessier!
      ```
      
      ---------------------------------------------------------------------
      
      llvm-svn: 314464
      3c3efb4e
    • Tom Stellard's avatar
      Merging r313998: · a9ebe385
      Tom Stellard authored
      ```---------------------------------------------------------------------
      r313998 | bmakam | 2017-09-22 10:46:36 -0700 (Fri, 22 Sep 2017) | 3 lines
      
          [Falkor] Add falkor CPU to host detection
      
          This returns "falkor" for Falkor CPU.
      ```
      
      ---------------------------------------------------------------------
      
      llvm-svn: 314437
      a9ebe385
    • Tom Stellard's avatar
      Merging r312622: · 7c188fa8
      Tom Stellard authored
      ```---------------------------------------------------------------------
      r312622 | jbcoe | 2017-09-06 00:33:32 -0700 (Wed, 06 Sep 2017) | 13 lines
      
      Fix __repr__ for Diagnostic in clang.cindex
      
      Summary: Also move misplaced tests for exception specification to fix failing Python tests.
      
      Reviewers: hans, compnerd
      
      Reviewed By: compnerd
      
      Subscribers: cfe-commits
      
      Tags: #clang-c
      
      Differential Revision: https://reviews.llvm.org/D37490
      ```
      
      ---------------------------------------------------------------------
      
      llvm-svn: 314434
      7c188fa8
    • Joerg Sonnenberger's avatar
      Merging r311921: · 722d0d27
      Joerg Sonnenberger authored
      ```---------------------------------------------------------------------
      r311921 | joerg | 2017-08-28 22:20:47 +0200 (Mon, 28 Aug 2017) | 16 lines
      
      Fix ARMv4 support
      
      ARMv4 doesn't support the "BX" instruction, which has been introduced
      with ARMv4t. Adjust the call lowering and tail call implementation
      accordingly.
      
      Further changes are necessary to ensure that presence of the v4t feature
      is correctly set. Most importantly, the "generic" CPU for thumb-*
      triples should include ARMv4t, since thumb mode without thumb support
      would naturally be pointless.
      
      Add a couple of asserts to ensure thumb instructions are not emitted
      without CPU support.
      
      Differential Revision: https://reviews.llvm.org/D37030
      ```
      
      ---------------------------------------------------------------------
      
      llvm-svn: 314417
      722d0d27
    • Dylan McKay's avatar
      Merging r314180: · c2f252c4
      Dylan McKay authored
      ```---------------------------------------------------------------------
      r314180 | dylanmckay | 2017-09-26 13:51:03 +1300 (Tue, 26 Sep 2017) | 7 lines
      
      [AVR] When lowering shifts into loops, put newly generated MBBs in the same
      spot as the original MBB
      
      Discovered in avr-rust/rust#62
      https://github.com/avr-rust/rust/issues/62
      
      Patch by Gergo Erdi.
      ```
      
      ---------------------------------------------------------------------
      
      llvm-svn: 314383
      c2f252c4
    • Dylan McKay's avatar
      Merging r314183: · 6058b5f9
      Dylan McKay authored
      ```---------------------------------------------------------------------
      r314183 | dylanmckay | 2017-09-26 15:07:54 +1300 (Tue, 26 Sep 2017) | 3 lines
      
      [AVR] Fix the build after setting alignment to 1 in r314179
      
      Changing all types to be byte-aligned broke a small number of tests.
      ```
      
      ---------------------------------------------------------------------
      
      llvm-svn: 314382
      6058b5f9
    • Dylan McKay's avatar
      Merging r314354: · bb93923a
      Dylan McKay authored
      ```---------------------------------------------------------------------
      r314354 | dylanmckay | 2017-09-28 11:09:01 +1300 (Thu, 28 Sep 2017) | 3 lines
      
      [AVR] Update data layout to match current LLVM trunk
      
      The data layout was changed in r314179 to fix atomic loads and stores.
      ```
      
      ---------------------------------------------------------------------
      
      llvm-svn: 314381
      bb93923a
    • Dylan McKay's avatar
      Merging r314179: · 749ebdf7
      Dylan McKay authored
      ```---------------------------------------------------------------------
      r314179 | dylanmckay | 2017-09-26 13:45:27 +1300 (Tue, 26 Sep 2017) | 11 lines
      
      [AVR] Use 1-byte alignment for all data types
      
      This was an oversight in the original backend data layout.
      
      The AVR architecture does not have the concept of unaligned loads - all
      loads/stores from all addresses are aligned to one byte.
      
      Discovered in avr-rust issue #64
      https://github.com/avr-rust/rust/issues/64
      
      Patch By Gergo Erdi.
      ```
      
      ---------------------------------------------------------------------
      
      llvm-svn: 314379
      749ebdf7
  13. 27 Sep, 2017 6 commits
    • Dylan McKay's avatar
      Merging r311620: · 0200f2bf
      Dylan McKay authored
      ```---------------------------------------------------------------------
      r311620 | dylanmckay | 2017-08-24 12:14:38 +1200 (Thu, 24 Aug 2017) | 1 line
      
      [AVR] Use the correct register classes for 16-bit atomic operations
      ```
      
      ---------------------------------------------------------------------
      
      llvm-svn: 314358
      0200f2bf
    • Dylan McKay's avatar
      Merging r314070: · 51d99153
      Dylan McKay authored
      ```---------------------------------------------------------------------
      r314070 | dylanmckay | 2017-09-24 14:07:26 +1300 (Sun, 24 Sep 2017) | 6 lines
      
      [AVR] Implement getCmpLibcallReturnType().
      
      This fixes the avr-rust issue (#75) with floating-point comparisons generating broken code.
      By default, LLVM assumes these comparisons return 32-bit values, but ours are 8-bit.
      
      Patch By Thomas Backman.
      ```
      
      ---------------------------------------------------------------------
      
      llvm-svn: 314357
      51d99153
    • Dylan McKay's avatar
      Merging r312905: · 34c887f1
      Dylan McKay authored
      ```---------------------------------------------------------------------
      r312905 | dylanmckay | 2017-09-11 22:32:51 +1200 (Mon, 11 Sep 2017) | 10 lines
      
      [AVR] Enable the '__do_copy_data' function
      
      Also enables '__do_clear_bss'.
      
      These functions are automaticalled called by the CRT if they are
      declared.
      
      We need these to be called otherwise RAM will start completely
      uninitialised, even though we need to copy RAM variables from progmem to
      RAM.
      ```
      
      ---------------------------------------------------------------------
      
      llvm-svn: 314356
      34c887f1
    • Tom Stellard's avatar
      Merging r312337: · 7f6d22cd
      Tom Stellard authored
      ```---------------------------------------------------------------------
      r312337 | nha | 2017-09-01 09:56:32 -0700 (Fri, 01 Sep 2017) | 12 lines
      
      AMDGPU: IMPLICIT_DEFs and DBG_VALUEs do not contribute to wait states
      
      Summary:
      This fixes a bug that was exposed on gfx9 in various
      GL45-CTS.shaders.loops.*_iterations.select_iteration_count_fragment tests,
      e.g. GL45-CTS.shaders.loops.do_while_uniform_iterations.select_iteration_count_fragment
      
      Reviewers: arsenm
      
      Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
      
      Differential Revision: https://reviews.llvm.org/D36193
      ```
      
      ---------------------------------------------------------------------
      
      llvm-svn: 314327
      7f6d22cd
    • Tom Stellard's avatar
      Revert "Merging r312337:" · 14adbd0d
      Tom Stellard authored
      This reverts commit r314324.
      
      I unintentionally deleted most of the svn:mergeinfo for the release_50
      branch with this commit.
      
      llvm-svn: 314326
      14adbd0d
    • Tom Stellard's avatar
      Merging r312337: · 95eb0d94
      Tom Stellard authored
      ```---------------------------------------------------------------------
      r312337 | nha | 2017-09-01 09:56:32 -0700 (Fri, 01 Sep 2017) | 12 lines
      
      AMDGPU: IMPLICIT_DEFs and DBG_VALUEs do not contribute to wait states
      
      Summary:
      This fixes a bug that was exposed on gfx9 in various
      GL45-CTS.shaders.loops.*_iterations.select_iteration_count_fragment tests,
      e.g. GL45-CTS.shaders.loops.do_while_uniform_iterations.select_iteration_count_fragment
      
      Reviewers: arsenm
      
      Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
      
      Differential Revision: https://reviews.llvm.org/D36193
      ```
      
      ---------------------------------------------------------------------
      
      llvm-svn: 314324
      95eb0d94
  14. 15 Sep, 2017 2 commits
    • Tom Stellard's avatar
      Bump version to 5.0.1 · ddd861d8
      Tom Stellard authored
      llvm-svn: 313339
      ddd861d8
    • Tom Stellard's avatar
      Merging r313334: · 6442f8f8
      Tom Stellard authored
      ```---------------------------------------------------------------------
      r313334 | tstellar | 2017-09-14 19:25:22 -0700 (Thu, 14 Sep 2017) | 15 lines
      
      merge-request.sh: Update to use new "Fixed by Commit(s)" field
      
      Summary:
      This will be used instead of the url field to track which commits need
      to be merged.
      
      This patch also drops support for version 1.x of the bugzilla CLI tool.
      
      Reviewers: hansw, hans
      
      Reviewed By: hans
      
      Subscribers: hans, llvm-commits
      
      Differential Revision: https://reviews.llvm.org/D37786
      ```
      
      ---------------------------------------------------------------------
      
      llvm-svn: 313337
      6442f8f8